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2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)最新文献

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A power-supply noise aware dynamic timing analysis methodology, based on a statistical prediction engine 基于统计预测引擎的电源噪声感知动态时序分析方法
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-09 DOI: 10.1109/DTIS.2018.8368570
M. Tsiampas, N. Evmorfopoulos, Konstantis Daloukas, J. Moondanos, G. Stamoulis
{"title":"A power-supply noise aware dynamic timing analysis methodology, based on a statistical prediction engine","authors":"M. Tsiampas, N. Evmorfopoulos, Konstantis Daloukas, J. Moondanos, G. Stamoulis","doi":"10.1109/DTIS.2018.8368570","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368570","url":null,"abstract":"As technologies continue to shrink, industry seeks even faster ultra-low power ICs, requiring more accurate estimation of the worst case delay. Although traditional Static Timing Analysis (STA) methods incorporate data regarding interconnects and noise over power supply networks, they are still considered to be overly pessimistic. The only way to accurately capture dynamic effects in the estimation of the worst case delay is through Dynamic Timing Analysis (DTA). In this paper we propose a novel methodology to precisely estimate a tight upper bound of the worst case delay, using Extreme Value Theory on the results of voltage drop-aware simulation.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126538558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Give me your binary, I'll tell you if it leaks 把你的二进制文件给我，如果泄露了我会告诉你
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-09 DOI: 10.1109/DTIS.2018.8368582
Antoine Bouvet, Nicolas Bruneau, A. Facon, S. Guilley, Damien Marion
{"title":"Give me your binary, I'll tell you if it leaks","authors":"Antoine Bouvet, Nicolas Bruneau, A. Facon, S. Guilley, Damien Marion","doi":"10.1109/DTIS.2018.8368582","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368582","url":null,"abstract":"In this paper we present a method to identify side-channel information leakage of a cryptosystem software implementation, which is performed at the binary level, and needs only a debugger. Using a new resynchronization method based on the control flow, leaking instructions are retrieved with only few traces and without leakage model. Advantageously this methodology is target agnostic, finding the side-channel leakages without the need to know how the software will be used.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115060128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Is aproximate computing suitable for selective hardening of arithmetic circuits? 近似计算适用于算术电路的选择性硬化吗?
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-09 DOI: 10.1109/DTIS.2018.8368559
B. Deveautour, A. Virazel, P. Girard, S. Pravossoudovitch, V. Gherman
{"title":"Is aproximate computing suitable for selective hardening of arithmetic circuits?","authors":"B. Deveautour, A. Virazel, P. Girard, S. Pravossoudovitch, V. Gherman","doi":"10.1109/DTIS.2018.8368559","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368559","url":null,"abstract":"Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. In this paper, we address the problem of selective hardening of arithmetic circuits by considering a duplication/comparison scheme as error detection architecture. Different duplication scenarios have been investigated: i) a full duplication, ii) a reduced duplication based on a structural susceptibility analysis, iii) a reduced duplication based on the logical weight of the arithmetic circuit outputs and iv) a reduced duplication based on an approximated structure from a public benchmark suite. Experimental results performed on adder and multiplier case study circuits demonstrate the interest of using approximate circuits to improve the mean time to failure while keeping a low area and power overhead and reduced error probability and error magnitude.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131695022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The test cost reduction benefits of combining a hierarchical DFT methodology with EDT channel sharing — A case study 将分层DFT方法与EDT信道共享相结合的测试成本降低-一个案例研究
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-09 DOI: 10.1109/DTIS.2018.8368556
Binghua Lu, Selina Sha, Jincheng Wang, Zhigao Zhang, Fanjin Meng, D. Hsu, R. Fisette
{"title":"The test cost reduction benefits of combining a hierarchical DFT methodology with EDT channel sharing — A case study","authors":"Binghua Lu, Selina Sha, Jincheng Wang, Zhigao Zhang, Fanjin Meng, D. Hsu, R. Fisette","doi":"10.1109/DTIS.2018.8368556","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368556","url":null,"abstract":"This paper describes how two Design-For-Test (DFT) techniques (hierarchical methodology and Embedded Deterministic Test (EDT) channel sharing) were combined on an industrial design to reduce test cost factors such as ATPG runtime, ATPG memory footprint, and manufacturing test time as well as reduce overall DFT schedule.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"6 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116818190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Wireless sEMG/footswitch driven FPGA embedded digital processor for dynamic MFCV estimation 用于动态MFCV估计的无线sEMG/脚踏开关驱动FPGA嵌入式数字处理器
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-09 DOI: 10.1109/DTIS.2018.8368575
G. Mezzina, D. Venuto
{"title":"Wireless sEMG/footswitch driven FPGA embedded digital processor for dynamic MFCV estimation","authors":"G. Mezzina, D. Venuto","doi":"10.1109/DTIS.2018.8368575","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368575","url":null,"abstract":"This paper proposes the design and the implementation of an FPGA-based Cyber-physical system for the real-time monitoring of the Muscle Fiber Conduction Velocity (MFCV). The MFCV is evaluated during the walking by using of 4 wireless surface EMG electrodes, and 2 footswitches. The implemented algorithm, for the MFCV assessment, is based on the extraction of the degree of resemblance between 2 EMG signals from the same leg. The processor architecture has been fully implemented on FPGA. The system data transmission is entrusted to a Bluetooth module, which connects the FPGA to an external device. The complete system occupies 12% ALMs, 5903 ALUTs, 5% registers, 3.28% block memory, provide of the Altera Cyclone V. The computation time is respectively 125ns for the footswitch and 316ms for the EMG data, while 63.5±0.25ms are spent for the processing and MFCV evaluation. The technique has been validated on 6 subjects and the measurement results are here reported. The in-vivo measures agree with the clinical results, providing an MFCV=7.6m/s±0.36m/s, i.e., <0.1m/s w.r.t. typical value, for healthy subjects in the same operating conditions.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128898271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel MAC protocol for industrial WLAN: Hardware aspects 一种新的工业无线局域网MAC协议:硬件方面
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-09 DOI: 10.1109/DTIS.2018.8368580
Z. Stamenkovic
{"title":"A novel MAC protocol for industrial WLAN: Hardware aspects","authors":"Z. Stamenkovic","doi":"10.1109/DTIS.2018.8368580","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368580","url":null,"abstract":"The tutorial introduces a novel Medium Access Control (MAC) protocol for industrial Wireless Local Area Networks (WLANs). This protocol provides the ultra-low network latency with a target upper bound in the order of 1 ms while maintaining a high network reliability and availability. The novelty of the proposed wireless MAC protocol resides in its similar latency performance as its counterpart in industrial wired LANs. First, the functional design of the MAC protocol is described. Then, its performance results gained from a hardware implementation (SystemC and VHDL) on an FPGA platform are presented. Architecture and implementation details of the MAC processor including system simulation and test procedures are described. Finally, a real-time communication module which achieves the ultra-low latency required in industrial automation is presented.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133340754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reconfigurable electrostatically doped 2.5-gate planar field-effect transistors for dopant-free CMOS 用于无掺杂CMOS的可重构静电掺杂2.5栅极平面场效应晶体管
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-09 DOI: 10.1109/DTIS.2018.8368567
Tillmann A. Krauss, Frank Wessely, U. Schwalke
{"title":"Reconfigurable electrostatically doped 2.5-gate planar field-effect transistors for dopant-free CMOS","authors":"Tillmann A. Krauss, Frank Wessely, U. Schwalke","doi":"10.1109/DTIS.2018.8368567","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368567","url":null,"abstract":"In this paper, we demonstrate by extending TCAD simulations based on experimental data of fabricated electrostatically doped, reconfigurable planar double-gate field-effect transistors, the improved characteristics of a triple gate device design. The technological cornerstones for this general-purpose FET comprise mid-gap Schottky S/D junctions on a silicon-on-insulator substrate. The transistor type, i.e. n-type or p-type, is interchangeable during operation by applying a control-gate voltage which significantly increases the flexibility and versatility in the design of integrated circuits.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114995492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Increasing reliability of safety critical applications through functional based solutions 通过基于功能的解决方案提高安全关键应用的可靠性
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-09 DOI: 10.1109/DTIS.2018.8368555
E. Sánchez
{"title":"Increasing reliability of safety critical applications through functional based solutions","authors":"E. Sánchez","doi":"10.1109/DTIS.2018.8368555","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368555","url":null,"abstract":"In this paper, the author provides a brief guideline to effectively generate and run test programs for microprocessor-based systems running safety-critical applications. The most important constraints that need to be considered during the generation phase, as well as during the execution time are described. Additionally, a comparison is provided by checking three different SBST strategies on a particular module of a pipelined processor core.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117039152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells 温度对DICE和6T-SRAM细胞SEU易损性影响的评价
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-09 DOI: 10.1109/DTIS.2018.8368578
Emna Farjallah, V. Gherman, J. Armani, L. Dilillo
{"title":"Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells","authors":"Emna Farjallah, V. Gherman, J. Armani, L. Dilillo","doi":"10.1109/DTIS.2018.8368578","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368578","url":null,"abstract":"In this paper, we evaluate the temperature influence on the vulnerability to single event upsets (SEU) of 6-transistor static random access memory (6T-SRAM) cells and dual interlocked storage cells (DICE). The critical charge (Qcrit, minimum charge capable of generating an SEU) is evaluated for 65nm, 45nm, 32nm and 22nm bulk CMOS technologies and temperatures between −50°C and 150°C. A double exponential signal is used to model the current pulse generated by ionizing particles. SPICE simulations have shown that Qcrit is sensibly reduced by the rise of temperature. Qcrit variations of up to 88.4% and 99.9% have been calculated for 6T-SRAM and DICE cells, respectively.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124608393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Memristor based adaptive impedance and frequency tuning network 基于忆阻器的自适应阻抗和频率调谐网络
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-09 DOI: 10.1109/DTIS.2018.8368553
C. L. Palson, D. D. Krishna, J. Mathew, B. R. Jose, M. Ottavi, Vishal Gupta, Vishal Gupta
{"title":"Memristor based adaptive impedance and frequency tuning network","authors":"C. L. Palson, D. D. Krishna, J. Mathew, B. R. Jose, M. Ottavi, Vishal Gupta, Vishal Gupta","doi":"10.1109/DTIS.2018.8368553","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368553","url":null,"abstract":"Memristors have been recently proposed as an alternative solution to incorporate switched behavior along with traditional CMOS circuits. Furthermore, with the advent of technology, adaptive impedance and frequency tuning is essential in communication devices. To enable both tuning, a matching network based on switchable capacitors with fixed inductors is proposed in this paper. Here, switching is done by means of memristive switches. This paper analyzes the working of memristor as a switch and a matching network based on memristors which adaptively tunes with impedance and frequency. With 3 capacitor banks of each 0.5 pF resolution and 2 fixed inductors, matching for antenna impedance ranging from 20 to 200 Ohms and for frequencies ranging from 0.9 to 3.2 GHz is reported.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124489127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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