将分层DFT方法与EDT信道共享相结合的测试成本降低-一个案例研究

2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-09 DOI:10.1109/DTIS.2018.8368556

Binghua Lu, Selina Sha, Jincheng Wang, Zhigao Zhang, Fanjin Meng, D. Hsu, R. Fisette

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引用次数: 2

摘要

本文描述了如何将两种面向测试的设计(DFT)技术(分层方法和嵌入式确定性测试(EDT)通道共享)结合到工业设计中，以减少测试成本因素，如ATPG运行时间、ATPG内存占用和制造测试时间，以及减少总体DFT时间表。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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The test cost reduction benefits of combining a hierarchical DFT methodology with EDT channel sharing — A case study

This paper describes how two Design-For-Test (DFT) techniques (hierarchical methodology and Embedded Deterministic Test (EDT) channel sharing) were combined on an industrial design to reduce test cost factors such as ATPG runtime, ATPG memory footprint, and manufacturing test time as well as reduce overall DFT schedule.

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来源期刊

2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)

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