The test cost reduction benefits of combining a hierarchical DFT methodology with EDT channel sharing — A case study

Abstract

This paper describes how two Design-For-Test (DFT) techniques (hierarchical methodology and Embedded Deterministic Test (EDT) channel sharing) were combined on an industrial design to reduce test cost factors such as ATPG runtime, ATPG memory footprint, and manufacturing test time as well as reduce overall DFT schedule.