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2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)最新文献

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Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering 基于radix-43算法的二维FFT结构，具有高效的输出重排序
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-09 DOI: 10.1109/DTIS.2018.8368562
S. Kala, N. Sivanandan, B. R. Jose, J. Mathew, M. Ottavi
{"title":"Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering","authors":"S. Kala, N. Sivanandan, B. R. Jose, J. Mathew, M. Ottavi","doi":"10.1109/DTIS.2018.8368562","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368562","url":null,"abstract":"In this paper we present a 64 × 64-point 2D FFT architecture using a parallel unrolled radix-4<sup>3</sup> (R4<sup>3</sup>) FFT as the basic block. Our R4<sup>3</sup> architecture is a memory optimized parallel architecture which computes 64-point FFT, with least execution time. Here we use row-column decomposition of two R4<sup>3</sup> blocks to compute a 2D FFT. Proposed architecture has been implemented in UMC 40nm CMOS technology with clock frequency of 500 MHz, area of 0.841mm<sup>2</sup> and power consumption of 358 mW. Computation time of 64 × 64 FFT is 8.19μs. ASIC results shows better performance of our FFT in terms of computation time when compared with state-of-art implementation.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116431162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Towards a scalable quantum computer 向着可扩展的量子计算机迈进
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-09 DOI: 10.1109/DTIS.2018.8368579
C. G. Almudever, N. Khammassi, L. Hutin, M. Vinet, M. Babaie, F. Sebastiano, E. Charbon, K. Bertels
{"title":"Towards a scalable quantum computer","authors":"C. G. Almudever, N. Khammassi, L. Hutin, M. Vinet, M. Babaie, F. Sebastiano, E. Charbon, K. Bertels","doi":"10.1109/DTIS.2018.8368579","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368579","url":null,"abstract":"A quantum machine may solve some complex problems that are intractable for even the most powerful classical computers. By exploiting quantum superposition and entanglement phenomena, quantum algorithms can achieve from polynomial to exponential speed up when compared to their best classical counterparts. A quantum computer will be a part of a heterogeneous, multi-core computer in which a classical processor will interact with several accelerators such as FPGAs, GPUs and also a quantum co-processor. Figure 1 shows the different layers of the quantum computer system stack [1]. Building such a quantum system requires contributions from different fields such as physics, electronics, computer science and computer engineering for addressing the following challenges: i) build scalable quantum chips integrating qubits with long coherence times and high-fidelity operations, ii) develop classical control electronics at possibly cryogenic temperatures and iii) create the microarchitecture as well as the software for quantum computation.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132914465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Dynamic partial reconfiguration verification using assertion based verification
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-01 DOI: 10.1109/DTIS.2018.8368552
Islam Ahmed, H. Mostafa, A. Mohieldin
{"title":"Dynamic partial reconfiguration verification using assertion based verification","authors":"Islam Ahmed, H. Mostafa, A. Mohieldin","doi":"10.1109/DTIS.2018.8368552","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368552","url":null,"abstract":"Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows reconfiguration of some of the logic at runtime while the rest of the logic keeps operating. This feature allows the designers to build complex systems such as Software Defined Radio (SDR) in a reasonable area. However, utilizing DPR needs extra care to be taken for new issues such as waiting for running computations on a module before reconfiguring it, isolation of the reconfigurable modules during the reconfiguration process, and initialization of the reconfigurable module after the reconfiguration process is done. This paper proposes a technique to verify these newly introduced issues using Assertion Based Verification (ABV). The proposed technique proves effectiveness in finding issues on real designs that utilize DPR technique.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127106676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 1Kx32 bit WDSRAM page with rapid write access 具有快速写访问的1Kx32位WDSRAM页面
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-01 DOI: 10.1109/DTIS.2018.8368584
Theodoros Simopoulos, T. Haniotakis, G. Alexiou
{"title":"A 1Kx32 bit WDSRAM page with rapid write access","authors":"Theodoros Simopoulos, T. Haniotakis, G. Alexiou","doi":"10.1109/DTIS.2018.8368584","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368584","url":null,"abstract":"In this work we present the hierarchical implementation of a 1Kx32 bit SRAM page which supports the WDSRAM — Write Driver SRAM — enhancements. The creation of the double-rows of the page's architectural scheme and the I/O tunnel between them is explained. The paper concludes with the presentation of the post-layout simulation results which confirm the fast write operation of the WDSRAM on the memory page level.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130830391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Programmable logic for single-output functions 可编程逻辑的单输出功能
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-01 DOI: 10.1109/DTIS.2018.8368581
I. Voyiatzis, C. Efstathiou, C. Sgouropoulou
{"title":"Programmable logic for single-output functions","authors":"I. Voyiatzis, C. Efstathiou, C. Sgouropoulou","doi":"10.1109/DTIS.2018.8368581","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368581","url":null,"abstract":"Single output functions have gained attention due to the popularity of FPGAs that implement complicated circuits based on Look-Up Tables (LUTs). LUTs implement single-output modules using multiplexer-based designs. In this work we present a scheme for the implementation of programmable single output functions. The proposed design can be utilized to implement LUTs with lower overhead compared to traditional designs with gate-based multiplexers.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128099147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evaluation of a median threshold based EEPROM-PUF concept implemented in a high temperature SOI CMOS technology 基于中值阈值的EEPROM-PUF概念在高温SOI CMOS技术中实现的评估
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-01 DOI: 10.1109/DTIS.2018.8368576
Benjamin Willsch, Marius te Heesen, J. Hauser, S. Dreiner, H. Kappert, H. Vogt
{"title":"Evaluation of a median threshold based EEPROM-PUF concept implemented in a high temperature SOI CMOS technology","authors":"Benjamin Willsch, Marius te Heesen, J. Hauser, S. Dreiner, H. Kappert, H. Vogt","doi":"10.1109/DTIS.2018.8368576","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368576","url":null,"abstract":"Physically Unclonable Functions (PUFs) are a new type of hardware-bounded cryptographic primitives. PUFs leverage random process variations to generate unique keys suitable for the use in low-cost device identification and authentication applications. Since the keys are typically derived from a large number of semiconductor devices, a space- and power-saving implementation of PUFs in non-volatile memory is appealing. In this paper, a median threshold based PUF concept was experimentally evaluated for 68 EEPROM arrays fabricated in a high temperature 1 ßm SOI CMOS technology. As-is realization of the concept yielded poor results regarding the randomness and uniqueness of the generated keys featuring an average inter-Hamming distance of only 30.24% (ideal value: 50%). The observed bias could be attributed to the presence of systematic trends induced by an asymmetric cell layout of the EEPROM arrays. To mitigate the effect of systematic process variations, a simple optimization procedure is proposed that has significantly increased the average inter-Hamming distance by more than 18 percentage points.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121717779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low-energy key exchange for automation systems 自动化系统的低能耗钥匙交换
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-01 DOI: 10.1109/DTIS.2018.8368586
D. Kreiser, Z. Dyka, I. Kabin, P. Langendörfer
{"title":"Low-energy key exchange for automation systems","authors":"D. Kreiser, Z. Dyka, I. Kabin, P. Langendörfer","doi":"10.1109/DTIS.2018.8368586","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368586","url":null,"abstract":"There is a clear trend towards the use of wireless communication in automation systems (AS). To make wireless communication systems usable for automation systems, it is crucial that they fulfil the strong requirements with respect to latency and security. For ensuring security features such as confidentiality and data integrity cipher algorithms are used. In this paper we focus on the most important operation in crypto-systems i.e. the key distribution. As the major part of the devices is resource constraint, energy efficiency is of utmost importance. In this paper we propose to combine the EC ElGamal encryption approach corresponding to [1] with the Montgomery kP algorithm using projective Lopez-Dahab coordinates [4] for realizing the key exchange. The proposed combination helps to reduce the energy needed for exchanging a shared secret key by 30%. This is mainly achieved by reducing the number of bits to be transmitted.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133518854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Towards novel format for representation of polymorphic circuits 多态电路表示的新格式
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-01 DOI: 10.1109/DTIS.2018.8368583
Adam Crha, Václav Simek, R. Ruzicka
{"title":"Towards novel format for representation of polymorphic circuits","authors":"Adam Crha, Václav Simek, R. Ruzicka","doi":"10.1109/DTIS.2018.8368583","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368583","url":null,"abstract":"This paper is focused on the introduction of a novel format for representation of complex polymorphic circuits. Core of this newly presented format is based on the exploitation of And-Inverter Graph (AIG) scheme with a number of extensions. Then, synthesis flow can exploit considerable advantages in terms of the capability to handle at ease more extensive circuit structures involving hundreds of gates and employ subsequent optimization techniques resulting in an improved area-efficiency performance. The actual format notation, explanation of its visual features appearance meaning and comparison with selected conventional approaches are presented. Finally, accomplished experimental results and their analysis is provided.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129389601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Unified field multiplier for ECC: Inherent resistance against horizontal SCA attacks 统一的域倍增器ECC:对横向SCA攻击的固有抵抗力
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-01 DOI: 10.1109/DTIS.2018.8368560
I. Kabin, Z. Dyka, D. Kreiser, P. Langendörfer
{"title":"Unified field multiplier for ECC: Inherent resistance against horizontal SCA attacks","authors":"I. Kabin, Z. Dyka, D. Kreiser, P. Langendörfer","doi":"10.1109/DTIS.2018.8368560","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368560","url":null,"abstract":"In this paper we introduce a unified field multiplier for the EC kP operation in two different types of Galois fields. The most important contributions of this paper are that the multiplier is based on the 4-segment Karatsuba multiplication method and that it is inherent resistant against selected horizontal attacks.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124659795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Cross-product functional coverage analysis using machine learning clustering techniques 使用机器学习聚类技术进行跨产品功能覆盖分析
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-01 DOI: 10.1109/DTIS.2018.8368574
Eman El Mandouh, A. Salem, Mennatallah Amer, A. Wassal
{"title":"Cross-product functional coverage analysis using machine learning clustering techniques","authors":"Eman El Mandouh, A. Salem, Mennatallah Amer, A. Wassal","doi":"10.1109/DTIS.2018.8368574","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368574","url":null,"abstract":"This work proposes the application of clustering machine learning to simplify functional coverage analysis. It introduces a two-round clustering algorithm to group the functional coverage goals that share similar cover items. In the first round, the associations between cover-crosses are encoded as a binary connectivity matrix. K-Means with Jaccard similarity is used to group highly correlated cover-crosses. In the second round, coverage ratio is used as the main measure to sub-group the clusters resulted from the first round. The resulted clusters are then analyzed to identify which cover-crosses mostly contribute to low coverage clusters. Dropping the number of cover-crosses to analyze into a limited number of representative buckets that can further be used by advanced analysis engines to help reach coverage closure faster.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132609691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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