{"title":"具有快速写访问的1Kx32位WDSRAM页面","authors":"Theodoros Simopoulos, T. Haniotakis, G. Alexiou","doi":"10.1109/DTIS.2018.8368584","DOIUrl":null,"url":null,"abstract":"In this work we present the hierarchical implementation of a 1Kx32 bit SRAM page which supports the WDSRAM — Write Driver SRAM — enhancements. The creation of the double-rows of the page's architectural scheme and the I/O tunnel between them is explained. The paper concludes with the presentation of the post-layout simulation results which confirm the fast write operation of the WDSRAM on the memory page level.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 1Kx32 bit WDSRAM page with rapid write access\",\"authors\":\"Theodoros Simopoulos, T. Haniotakis, G. Alexiou\",\"doi\":\"10.1109/DTIS.2018.8368584\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work we present the hierarchical implementation of a 1Kx32 bit SRAM page which supports the WDSRAM — Write Driver SRAM — enhancements. The creation of the double-rows of the page's architectural scheme and the I/O tunnel between them is explained. The paper concludes with the presentation of the post-layout simulation results which confirm the fast write operation of the WDSRAM on the memory page level.\",\"PeriodicalId\":328650,\"journal\":{\"name\":\"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DTIS.2018.8368584\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DTIS.2018.8368584","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this work we present the hierarchical implementation of a 1Kx32 bit SRAM page which supports the WDSRAM — Write Driver SRAM — enhancements. The creation of the double-rows of the page's architectural scheme and the I/O tunnel between them is explained. The paper concludes with the presentation of the post-layout simulation results which confirm the fast write operation of the WDSRAM on the memory page level.