Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering

In this paper we present a 64 × 64-point 2D FFT architecture using a parallel unrolled radix-4³ (R4³) FFT as the basic block. Our R4³ architecture is a memory optimized parallel architecture which computes 64-point FFT, with least execution time. Here we use row-column decomposition of two R4³ blocks to compute a 2D FFT. Proposed architecture has been implemented in UMC 40nm CMOS technology with clock frequency of 500 MHz, area of 0.841mm² and power consumption of 358 mW. Computation time of 64 × 64 FFT is 8.19μs. ASIC results shows better performance of our FFT in terms of computation time when compared with state-of-art implementation.