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2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)最新文献

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Device and circuit models of InAlN/GaN D- and dual-gate E-mode HEMTs for design and characterisation of monolithic NAND logic cell 用于单片NAND逻辑单元设计和表征的InAlN/GaN D型和双栅e型hemt的器件和电路模型
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-01 DOI: 10.1109/DTIS.2018.8368565
A. Chvála, L. Nagy, J. Marek, J. Priesol, D. Donoval, A. Šatka, M. Blaho, D. Gregušová, J. Kuzmík
{"title":"Device and circuit models of InAlN/GaN D- and dual-gate E-mode HEMTs for design and characterisation of monolithic NAND logic cell","authors":"A. Chvála, L. Nagy, J. Marek, J. Priesol, D. Donoval, A. Šatka, M. Blaho, D. Gregušová, J. Kuzmík","doi":"10.1109/DTIS.2018.8368565","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368565","url":null,"abstract":"In this paper, we present the monolithic integration of enhancement-mode and depletion-mode InAlN/GaN heterostructure high electron mobility transistors (HEMTs). The aim of the work is to show the results of the designed NAND logic cell which consists of the enhancement-mode dual-gate HEMT transistor and the depletion-mode HEMT transistor integrated onto a single die. We present well calibrated electrophysical models for 2-D device simulations employing Sentaurus Device from Synopsys. Sentaurus Device mixed-mode setup interconnects both transistor types to NAND logic cell circuit which allows analysis and characterization of the device as the complex system. New circuit nonlinear models of depletion-mode and dual-gate enhancement-mode HEMTs are proposed and calibrated by experimental results. The proposed models exhibit more accurate results. Good agreement between measurements and simulations confirms the validity of the proposed models and simulation methodology.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131065497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A resource-efficient FFT/IFFT architecture for PRIME PLC systems 用于PRIME PLC系统的资源高效FFT/IFFT架构
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-01 DOI: 10.1109/DTIS.2018.8368571
J. Yang, N. Tan, Ching-Kae Tzou
{"title":"A resource-efficient FFT/IFFT architecture for PRIME PLC systems","authors":"J. Yang, N. Tan, Ching-Kae Tzou","doi":"10.1109/DTIS.2018.8368571","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368571","url":null,"abstract":"This paper presents a resource-efficient real-valued fast Fourier transform (RFFT) and Hermitian symmetric inverse fast Fourier transform (HSIFFT) architecture for narrowband power line communication (N-PLC) systems. The proposed architecture has high flexibility and low complexity in control, and can be easily extended to different radices and points. Based on the structure, a novel FFT/IFFT processor is designed for PRIME (PoweRline Intelligent Metering Evolution) N-PLC systems.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131362694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A configurable operational amplifier based on oxide resistive RAMs 一种基于氧化阻性ram的可配置运算放大器
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-01 DOI: 10.1109/DTIS.2018.8368572
H. Aziza, C. Dufaza, A. Pérez
{"title":"A configurable operational amplifier based on oxide resistive RAMs","authors":"H. Aziza, C. Dufaza, A. Pérez","doi":"10.1109/DTIS.2018.8368572","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368572","url":null,"abstract":"This paper proposes a memristor-based operational amplifier design in which semiconductors resistors are suppressed and replaced by memristors. Such design is developed based on a calibrated memristor model, and offers dynamic configurabilty to realize different gains at reduced chip area.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116573451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of dynamic partial reconfiguration on CONNECT Network-on-Chip for FPGAs 动态部分重构对fpga连接片上网络的影响
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-01 DOI: 10.1109/DTIS.2018.8368587
Ramy Ahmed, H. Mostafa, A. Khalil
{"title":"Impact of dynamic partial reconfiguration on CONNECT Network-on-Chip for FPGAs","authors":"Ramy Ahmed, H. Mostafa, A. Khalil","doi":"10.1109/DTIS.2018.8368587","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368587","url":null,"abstract":"This work presents the Dynamic Partial Reconfiguration (DPR) support to CONNECT Network-on-Chip (NoC) and studies its impact on the network performance. Runtime reconfigurability expands the flexibility of NoCs and allows a full customization for the dynamic reconfigurable applications. In comparison with the fixed NoCs, the runtime reconfigurable NoCs result in area optimization by reusing a part of the network when idle during the runtime. A reconfiguration tool is developed which analyzes the user benchmarks in order to find the optimal network structure (configuration) for every benchmark.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121076449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Numerical approach to predict power device reliability 电力设备可靠性预测的数值方法
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-01 DOI: 10.1109/DTIS.2018.8368577
A. Sitta, S. Russo, G. Bazzano, D. Cavallaro, G. Greco, M. Calabretta
{"title":"Numerical approach to predict power device reliability","authors":"A. Sitta, S. Russo, G. Bazzano, D. Cavallaro, G. Greco, M. Calabretta","doi":"10.1109/DTIS.2018.8368577","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368577","url":null,"abstract":"The scope of this paper is to work out a predictive method to estimate the power device reliability under active cycle tests. The proposed method is able to predict, through a numerical model, the local maximum temperature during test. The results validation has been pursued correlating the numerical thermal maps results with the experimental temperature distribution obtained from an infra-red camera. Front metal ratcheting has been recognized as the main root cause of contact resistance degradation during the considered reliability test (Repetitive Avalanche). This failure mode is dependent on the temperature variation for cycle, by which it is possible to predict the device lifetime according to the Coffin-Manson fatigue model.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125310927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
SIC pair generation in near-optimal time with carry-look ahead adders 带进前加法器的近最优时间SIC配对生成
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-01 DOI: 10.1109/DTIS.2018.8368573
I. Voyiatzis, C. Efstathiou
{"title":"SIC pair generation in near-optimal time with carry-look ahead adders","authors":"I. Voyiatzis, C. Efstathiou","doi":"10.1109/DTIS.2018.8368573","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368573","url":null,"abstract":"Single Input Change (SIC) pairs, are pairs of patterns where exactly one bit flips between the two patterns of the pair and are valuable for the detection of robustly detectable stuck-open and delay faults. Therefore, the on-chip generation of SIC pairs has gained attention from a number of researchers. Previous schemes targeting the generation of SIC pairs utilizing adders affect the critical path of the adder, altering the timing characteristics of the circuit. In this paper a novel SIC pair generator is presented, based on a carry-look ahead adder. The proposed scheme imposes no intervention on the critical path of the adder, therefore its timing characteristics are not affected.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115072512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel hardware-accelerated real-time task scheduler based on robust earliest deadline algorithm 一种基于鲁棒最早截止日期算法的硬件加速实时任务调度程序
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-01 DOI: 10.1109/DTIS.2018.8368551
L. Kohútka, V. Stopjaková
{"title":"A novel hardware-accelerated real-time task scheduler based on robust earliest deadline algorithm","authors":"L. Kohútka, V. Stopjaková","doi":"10.1109/DTIS.2018.8368551","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368551","url":null,"abstract":"This paper presents novel design of a coprocessor that implements the existing task scheduling algorithm called Robust Earliest Deadline (RED). Thanks to the HW implementation, the scheduler operations are always completed in two clock cycles regardless of the number of tasks to be scheduled. Resource costs are evaluated by synthesis for Intel FPGA Cyclone V. Three different real-time task schedulers are compared: EDF-based scheduler suitable for hard real-time tasks only, GED-based scheduler suitable for soft real-time tasks only, and the proposed RED-based scheduler. The proposed scheduler handles deviations of task execution times better, achieves higher CPU utilization and can be used for scheduling of hard real-time, soft real-time and non-real-time tasks within one system, which was not possible with the former existing solutions.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132800361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility ISIS中子设施中COTS相机与sram的设置与实验结果分析
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-01 DOI: 10.1109/DTIS.2018.8368564
M. Ottavi, Dario Asciolla, Tiziano Fiorucci, Elena Grosso, Carla Marzullo, Alessandro Scaramella, Simone Stramaccioni, Alessia Zibecchi, C. Andreani, G. Cardarilli, C. Cazzaniga, L. Nunzio, R. Fazzolari, M. Re, P. Reviriego, G. Furano, R. Senesi
{"title":"Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility","authors":"M. Ottavi, Dario Asciolla, Tiziano Fiorucci, Elena Grosso, Carla Marzullo, Alessandro Scaramella, Simone Stramaccioni, Alessia Zibecchi, C. Andreani, G. Cardarilli, C. Cazzaniga, L. Nunzio, R. Fazzolari, M. Re, P. Reviriego, G. Furano, R. Senesi","doi":"10.1109/DTIS.2018.8368564","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368564","url":null,"abstract":"The study of the effects of neutrons induced errors in Commercial Off The Shelf (COTS) components is becoming increasingly important for terrestrial and avionics applications as their potential impact in terms of reliability and safety could be catastrophic. This paper describes the setup and the experimental analysis of neutron irradiation tests performed at the Rutherford Appleton Laboratories (ISIS) neutron accelerator on the NEMESYS (Neutron Effects on MEmory SYStems) platform, a project which has the goal of studying the effects of atmospheric neutrons on COTS components during the stratospheric flight of a balloon. The results of bit upsets on the COTS SRAM and COTS Camera obtained from the tests are discussed and correlated together with a discussion on the observed system Single Event Functional Interrupts (SEFIs) providing an overall characterization of the targeted COTS components as well as on the setup on NEMESYS.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134401004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An alytical modeling of response time and full well capacity of a pinned photo diode 钉住式光电二极管响应时间和满阱容量的分析模型
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) Pub Date : 2018-04-01 DOI: 10.1109/DTIS.2018.8368568
K. Akshay, P. R. Pillai, B. Bhuvan
{"title":"An alytical modeling of response time and full well capacity of a pinned photo diode","authors":"K. Akshay, P. R. Pillai, B. Bhuvan","doi":"10.1109/DTIS.2018.8368568","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368568","url":null,"abstract":"In this paper, we propose a time based approach to explain the behavior of a pinned photo diode both in intrinsic and extrinsic mode of operation. Based on this approach, analytical models for the response time and full well capacity are derived. The models show good agreement with the TCAD simulations. Further, the models derived are heavily dependent on the photocurrent parameter. So, the sensitivity of photocurrent to doping variations of the pinned photodiode for different junction depths is also studied with the help of TCAD simulations.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125096460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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