SIC pair generation in near-optimal time with carry-look ahead adders

Abstract

Single Input Change (SIC) pairs, are pairs of patterns where exactly one bit flips between the two patterns of the pair and are valuable for the detection of robustly detectable stuck-open and delay faults. Therefore, the on-chip generation of SIC pairs has gained attention from a number of researchers. Previous schemes targeting the generation of SIC pairs utilizing adders affect the critical path of the adder, altering the timing characteristics of the circuit. In this paper a novel SIC pair generator is presented, based on a carry-look ahead adder. The proposed scheme imposes no intervention on the critical path of the adder, therefore its timing characteristics are not affected.