Impact of dynamic partial reconfiguration on CONNECT Network-on-Chip for FPGAs

Abstract

This work presents the Dynamic Partial Reconfiguration (DPR) support to CONNECT Network-on-Chip (NoC) and studies its impact on the network performance. Runtime reconfigurability expands the flexibility of NoCs and allows a full customization for the dynamic reconfigurable applications. In comparison with the fixed NoCs, the runtime reconfigurable NoCs result in area optimization by reusing a part of the network when idle during the runtime. A reconfiguration tool is developed which analyzes the user benchmarks in order to find the optimal network structure (configuration) for every benchmark.