A power-supply noise aware dynamic timing analysis methodology, based on a statistical prediction engine

As technologies continue to shrink, industry seeks even faster ultra-low power ICs, requiring more accurate estimation of the worst case delay. Although traditional Static Timing Analysis (STA) methods incorporate data regarding interconnects and noise over power supply networks, they are still considered to be overly pessimistic. The only way to accurately capture dynamic effects in the estimation of the worst case delay is through Dynamic Timing Analysis (DTA). In this paper we propose a novel methodology to precisely estimate a tight upper bound of the worst case delay, using Extreme Value Theory on the results of voltage drop-aware simulation.