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2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)最新文献

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Ultra low power 12-Bit SAR ADC for wireless sensing applications 用于无线传感应用的超低功耗12位SAR ADC
2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593060
Raja Hari Gudlavalleti, S. C. Bose
{"title":"Ultra low power 12-Bit SAR ADC for wireless sensing applications","authors":"Raja Hari Gudlavalleti, S. C. Bose","doi":"10.1109/VLSI-SATA.2016.7593060","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593060","url":null,"abstract":"This paper presents a 12-bit SA-ADC for portable low power wireless sensor systems. The proposed SA-ADC operates for rail-to-rail input range and achieves low power consumption. Split capacitor array based DAC and a novel charge-integration based dynamic comparator are used for low power consumption of the ADC. Measured DNL and INL are -0.59/0.67 LSB and -1.2/1.33 LSB respectively. At sampling rate of 100-kS/s with 1.8-V supply, the ADC consumes only 2-μW power and achieves a SNDR of 64.42-dB, SFDR of 71.2-dB resulting in an FoM of 14-fJ/Conversion-step. The ADC core occupies an area of 0.238-mm2 and is fabricated in AMS 0.35-μm CMOS technology.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123540308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A hardware optimized low power RNM compensated three stage operational amplifier with embedded capacitance multiplier compensation 一种嵌入式电容乘法器补偿的硬件优化低功耗RNM补偿三级运算放大器
2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593038
K. Singh, Anu Gupta
{"title":"A hardware optimized low power RNM compensated three stage operational amplifier with embedded capacitance multiplier compensation","authors":"K. Singh, Anu Gupta","doi":"10.1109/VLSI-SATA.2016.7593038","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593038","url":null,"abstract":"This paper proposes a hardware optimized low power three stage compensated operational amplifier with a capability of driving a wide range of capacitive loads ranging from 200pF to 5nF. The amplifier is compensated by implementing Embedded Capacitance Multiplier (CM) Compensation on the outer Miller capacitor of traditional Reverse Nested Miller Compensation (RNMC) with a feed forward stage. This provides a unity gain bandwidth (UGB) greater than 1MHz and phase margin greater than 60° for the range of loads mentioned above. The circuit has a 100uW of DC power dissipation for a 2V supply. The proposed technique uses two compensation capacitances of 1pf and 500fF only. The design achieves a unity gain bandwidth of 9.227MHz at 500pF capacitive load. The simulation is carried for 180nm CMOS technology in Cadence Virtuoso environment.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115187694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Towards formal verification of adaptive cruise controller using SpaceEx 基于SpaceEx的自适应巡航控制器的正式验证
2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593042
A. Mishra, S. Roy
{"title":"Towards formal verification of adaptive cruise controller using SpaceEx","authors":"A. Mishra, S. Roy","doi":"10.1109/VLSI-SATA.2016.7593042","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593042","url":null,"abstract":"A formal mathematical model of an Adaptive Cruise Controller (ACC) in SpaceEx is presented with a view to formally verify it to ensure its safety critical behavior. SpaceEx (an academic open source tool) is a hybrid systems modeling and verification platform which employs efficient implementation of reachability and safety verification algorithms which are scalable under certain assumptions, to circumvent the difficult problem of formal verification of hybrid systems. In this paper, application of SpaceEx in the comprehensive verification of an Adaptive Cruise Controller for automobiles is presented.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116413638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and analysis of novel fuzzifer circuits in CMOS current mode approach 新型CMOS电流模模糊电路的设计与分析
2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593035
A. Gubbi, M. Deeksha
{"title":"Design and analysis of novel fuzzifer circuits in CMOS current mode approach","authors":"A. Gubbi, M. Deeksha","doi":"10.1109/VLSI-SATA.2016.7593035","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593035","url":null,"abstract":"In this paper, the hardware realization of the basic blocks of Fuzzy Inference System (FIS) using simplified inference mechanism circuits are designed and tested in Complementary Metal Oxide Semiconductor (CMOS) Current Mode (CM). These circuits are useful in fuzzy and neuro-fuzzy systems. FIS consists of three main functional blocks. The fuzzification block using Membership Function Generator Circuit (MFGC), rule evaluation and defuzzification. The circuits are designed using the Cadence Virtuoso Design environment in 180nm technology and tested using the Spectre tool. The responses of the circuits, for variations in different signal values are represented using characteristics obtained from spectre tool. The circuit delays and average power are calculated from transient responses with simulation matching the mathematical calculation.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129518624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Effect of split manufacturing on power supply requirements 拆分制造对电源需求的影响
2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593033
Sharath K. Rangan, Shazia Afreen, R. Srinivasan
{"title":"Effect of split manufacturing on power supply requirements","authors":"Sharath K. Rangan, Shazia Afreen, R. Srinivasan","doi":"10.1109/VLSI-SATA.2016.7593033","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593033","url":null,"abstract":"Split manufacturing has become one of the most important methods to effectively control malware insertion and IP piracy. 3D IC technologies are still in the nascent stage, but 2.5D IC technology is currently adopted by most fabrication facilities. While recent studies on split manufacturing have focused on graph theoretic algorithms to effect a minimum cut split, none of them have discussed the effect of circuit performance due to the splitting. In this paper we show that split manufacturing has an adverse effect on power supply requirement, if circuit performance metrics have to stay the same before and after splitting. In particular, we have shown that multiple power supplies are necessary if circuit performance metrics have to be satisfied before and after the splitting procedure.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124632973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
NEDA based hybrid architecture for DCT — HWT 基于NEDA的DCT - HWT混合架构
2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593026
Vidhya Chandran, I. Mamatha, Shikha Tripathi
{"title":"NEDA based hybrid architecture for DCT — HWT","authors":"Vidhya Chandran, I. Mamatha, Shikha Tripathi","doi":"10.1109/VLSI-SATA.2016.7593026","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593026","url":null,"abstract":"Transforms are used in many signal processing applications. The VLSI implementation of a hybrid architecture to compute 8-point discrete cosine transform and Haar wavelet transform is proposed. The architecture is developed using NEw Distributed Arithmetic (NEDA) which is an efficient method for implementing inner products without using multipliers and ROM. The architecture developed is coded using Verilog HDL, simulated in ModelSim 6.4 and implemented using Xilinx ISE 14.7. Further, the hybrid architecture is implemented in 0.18μm CMOS technology using Cadence RTL compiler. Compared to standalone architectures, proposed architecture has 77.92% saving in register utilization, 41.80% savings in LUT utilization and 27.55% savings in number of adders used. The results show that the architecture is better in terms of power, hardware resources and complexity compared to earlier architectures.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117258369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design and analysis of different low noise amplifiers in 2–3GHz 2-3GHz不同低噪声放大器的设计与分析
2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593039
B. Prameela, A. E. Daniel
{"title":"Design and analysis of different low noise amplifiers in 2–3GHz","authors":"B. Prameela, A. E. Daniel","doi":"10.1109/VLSI-SATA.2016.7593039","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593039","url":null,"abstract":"This paper presents the design and simulation of four basic Low Noise Amplifier topologies based on 180nm Silicon technology. A common source stage with inductive degeneration, a resistive feedback, a folded cascode and a cascode stage has been designed, simulated and the performance has been analyzed. The LNA's are designed to be stable in the 2-3GHz. Of the four topologies the cascode stage has a high gain of 19.84dB and a very low Noise Figure (NF) of 0.59dB at 2.5GHz and at a supply voltage of 2.5V. The cascode stage has a P1dB of -17.76dBm and IIP3 of -2.49dBm. The power consumption of the circuit is 18.875mW. The simulations are done in cadence virtuoso SpectreRF. The cascode stage with very low Noise figure and good gain can be used for wireless applications such as Global Positioning System (GPS), Wireless LAN, WCDMA etc.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122052641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Real time watermarking of grayscale images using integer DWT transform 利用整数DWT变换实现灰度图像的实时水印
2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593056
S. Sakthivel, A. Sankar
{"title":"Real time watermarking of grayscale images using integer DWT transform","authors":"S. Sakthivel, A. Sankar","doi":"10.1109/VLSI-SATA.2016.7593056","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593056","url":null,"abstract":"In this paper, 2D integer wavelet transform based watermarking is carried out for the grayscale image with its VLSI architectural implementations. In the 2D integer wavelet transformation the lifting scheme is adopted and the watermarking operation is carried out in the LL2 frequency subbands. The entire watermark embedding process and extraction process are modeled in MATLAB and analyzed against the signal processing attacks like compression, salt & pepper noise, rotation and Intensity transformation attacks. Finally the same algorithm is modeled using Verilog HDL and implemented using ALTERA QUARTUS-II.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125083707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Distance estimation and direction finding using I2C protocol for an auto-navigation platform 基于I2C协议的自动导航平台距离估计和测向
2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593061
R. K. Megalingam, Jeeba M. Varghese, S. Anil
{"title":"Distance estimation and direction finding using I2C protocol for an auto-navigation platform","authors":"R. K. Megalingam, Jeeba M. Varghese, S. Anil","doi":"10.1109/VLSI-SATA.2016.7593061","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593061","url":null,"abstract":"This paper presents an auto navigation platform in Arduino which uses the i2c protocol to interface a digital compass and a rotation encoder to calculate distance travelled and direction with respect to the Earth's magnetic field. The digital compass IC used here is the HMC6352, while the rotation encoder is designed with the help of a MOC7811 coupler IC. The compass contains complete 2-axis sensors, analog, and digital electronics and also contains all the firmware for heading computation and calibration. The rotation encoder is an electromechanical device which obtains the angular position of the motor shaft it is connected to and then converts this position into some analog or digital value. This is mostly done using optoelectronic sensors which provide electric pulses in response to some stimulus. We use this property of the device to accurately guide our auto navigated device to pre-determined distances.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130222117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A gain enhanced low voltage bulk driven pseudo-differential OTA design in CMOS 一种增益增强的CMOS低电压体驱动伪差分OTA设计
2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593045
Antaryami Panigrahi, Abhipsa Parhi
{"title":"A gain enhanced low voltage bulk driven pseudo-differential OTA design in CMOS","authors":"Antaryami Panigrahi, Abhipsa Parhi","doi":"10.1109/VLSI-SATA.2016.7593045","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593045","url":null,"abstract":"A 0.5V low voltage bulk driven pseudodifferential OTA is presented here. Cross coupling technique both at the gate and bulk level is used to increase the effective output resistance of the OTA core. The effective input transconductance is also improved to achieve the high gain. Theoretical analysis for the operation of the OTA is described and simulation is performed to confirm the operation. The simulation results show open loop gain to be 42 dB and UGB of 2.3 MHz and Phase Margin of 85°. The input referred noise is 3.3μV/√Hz, Slew Rate 4.64V/uSec for load of 1pF and 10kΩ. Simulated transient response shows, the OTA achieving full swing of 200mVp-p. The circuit is designed using 250nm twinwell CMOS and simulated using T-Spice and BSIM 3v3 model. The power dissipation of the proposed OTA is 6.4μWatts.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124751650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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