2-3GHz不同低噪声放大器的设计与分析

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI:10.1109/VLSI-SATA.2016.7593039

B. Prameela, A. E. Daniel

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引用次数: 6

摘要

本文介绍了基于180nm硅工艺的四种基本低噪声放大器拓扑结构的设计与仿真。设计并仿真了具有感应退化、电阻反馈、折叠级联和级联级联的共源级，并对其性能进行了分析。LNA被设计为在2-3GHz范围内保持稳定。在四种拓扑结构中，级联级在2.5GHz和2.5V电源电压下具有19.84dB的高增益和0.59dB的极低噪声系数(NF)。级联级的P1dB为-17.76dBm, IIP3为-2.49dBm。电路的功耗为18.875mW。模拟是在SpectreRF中完成的。该级联具有极低的噪声系数和良好的增益，可用于全球定位系统(GPS)、无线局域网、WCDMA等无线应用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design and analysis of different low noise amplifiers in 2–3GHz

This paper presents the design and simulation of four basic Low Noise Amplifier topologies based on 180nm Silicon technology. A common source stage with inductive degeneration, a resistive feedback, a folded cascode and a cascode stage has been designed, simulated and the performance has been analyzed. The LNA's are designed to be stable in the 2-3GHz. Of the four topologies the cascode stage has a high gain of 19.84dB and a very low Noise Figure (NF) of 0.59dB at 2.5GHz and at a supply voltage of 2.5V. The cascode stage has a P1dB of -17.76dBm and IIP3 of -2.49dBm. The power consumption of the circuit is 18.875mW. The simulations are done in cadence virtuoso SpectreRF. The cascode stage with very low Noise figure and good gain can be used for wireless applications such as Global Positioning System (GPS), Wireless LAN, WCDMA etc.

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2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)

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