一种嵌入式电容乘法器补偿的硬件优化低功耗RNM补偿三级运算放大器

K. Singh, Anu Gupta
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引用次数: 0

摘要

本文提出了一种硬件优化的低功耗三级补偿运算放大器,具有驱动200pF至5nF宽范围容性负载的能力。该放大器通过在传统的反向嵌套米勒补偿(RNMC)的外米勒电容上实现嵌入式电容乘法器(CM)补偿,并具有前馈级。这为上述负载范围提供了大于1MHz的单位增益带宽(UGB)和大于60°的相位裕度。该电路在2V电源下具有100uW的直流功耗。所提出的技术只使用两个补偿电容1pf和500fF。该设计在500pF电容负载下实现了9.227MHz的单位增益带宽。在Cadence Virtuoso环境下对180nm CMOS工艺进行了仿真。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A hardware optimized low power RNM compensated three stage operational amplifier with embedded capacitance multiplier compensation
This paper proposes a hardware optimized low power three stage compensated operational amplifier with a capability of driving a wide range of capacitive loads ranging from 200pF to 5nF. The amplifier is compensated by implementing Embedded Capacitance Multiplier (CM) Compensation on the outer Miller capacitor of traditional Reverse Nested Miller Compensation (RNMC) with a feed forward stage. This provides a unity gain bandwidth (UGB) greater than 1MHz and phase margin greater than 60° for the range of loads mentioned above. The circuit has a 100uW of DC power dissipation for a 2V supply. The proposed technique uses two compensation capacitances of 1pf and 500fF only. The design achieves a unity gain bandwidth of 9.227MHz at 500pF capacitive load. The simulation is carried for 180nm CMOS technology in Cadence Virtuoso environment.
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