2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)最新文献_第2页

Efficient Network on Chip (NoC) using heterogeneous circuit switched routers 采用异构电路交换路由器的高效片上网络(NoC)

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593043

Anuja Naik, T. K. Ramesh

{"title":"Efficient Network on Chip (NoC) using heterogeneous circuit switched routers","authors":"Anuja Naik, T. K. Ramesh","doi":"10.1109/VLSI-SATA.2016.7593043","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593043","url":null,"abstract":"Network-on-Chip (NoC) architecture in recent years has been considered as the overwhelming communication solution to provide scalability in multi core systems over traditional bus-based communication architecture. There is an increased use of multi-core with NoC in embedded systems solutions. Energy efficiency in the Network-on-Chip (NoC) is one of the key challenges as these embedded systems are typically battery-powered. Router architecture impacts the performance of NoC. With increased interest towards circuit-switched routers, in this paper, we have proposed an area and energy efficient 5-port, 4 Lane circuit switched router using a CLOS network which presents the advantages of area and energy efficiency. To further improve energy efficiency of NoC, we use a hybrid architecture by mixing buffered and bufferless routers. Our results shows that by using CLOS switch network, we can gain 32% reduction in area and 26% reduction in power compared to Crossbar switch of the same size. Our comparison of using an 8×8 mesh heterogeneous router topology shows a reduction of 3% to 18% in silicon area and 10% to 15% in total power using bufferless routers compared to a fully buffered configuration.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117042278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Ultra low power capacitive power management unit in 0:18μm CMOS 超低功耗电容式电源管理单元，0:18μm CMOS

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593057

S. K. Kasodniya, B. Mishra, N. Desai

引用次数: 2

CORDIC-based VLSI architecture for implementing CI-OFDM and its FPGA prototype 基于cordic实现CI-OFDM的VLSI架构及其FPGA原型

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593037

Vikas Kumar, K. C. Ray, Preetam Kumar

{"title":"CORDIC-based VLSI architecture for implementing CI-OFDM and its FPGA prototype","authors":"Vikas Kumar, K. C. Ray, Preetam Kumar","doi":"10.1109/VLSI-SATA.2016.7593037","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593037","url":null,"abstract":"Since decades, orthogonal frequency division multiplexing (OFDM) has been drawing its attention in the area of wireless and satellite communication systems such as IEEE 802.11 a/g/n, ADSL, WiMAX and DVB-T/SH. In these applications, OFDM has drawbacks of high Peak-to-Average Power Ratio (PAPR) and Inter carrier symbol interference (ISI). Recently, Carrier Interferometry OFDM (CI-OFDM) as an alternative to OFDM is being studied to minimize the aforesaid drawbacks. To the knowledge of authors, there is no Field Programmable Gate Array (FPGA) prototyping of CI-OFDM is addressed for real time wireless and satellite communication system. In this context, authors in this paper have proposed a new hardware efficient and flexible CO-ordinate Rotational Digital Computer (CORDIC) based CI-OFDM architecture. The novelty of this proposed architecture is its capability to change the number of orthogonal subcarriers and data symbols upto the maximum 32K, that shall be suitable for most of the standards of wireless and satellite communication system and prototyped using commercially available FPGA device XC3S500E-5FG320. The implementation and experimental results of this proposed scheme are highlighted and validated with the result from MATLAB simulation.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"2022 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134298111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Switching based evaluation of substrate current in lightly and heavily doped CMOS at 45nm 基于开关的45nm轻掺杂和重掺杂CMOS衬底电流评估

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593058

Sanjay Sharma, R. P. Yadav, V. Janyani

引用次数: 0

FPGA implementation of face recognition system using efficient 5/3 2D-lifting scheme FPGA实现人脸识别系统采用高效的5/3 2d提升方案

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593025

Satish S. Bhairannawar, Rajath Kumar, Varsha Mirji, P. Sindhu

引用次数: 4

Mathematical modeling and analysis of new modified glitch free adiabatic inverter circuit with trapezoidal power supply 新型改进型梯形电源无故障绝热逆变电路的数学建模与分析

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593062

A. Majumder, R. Kaushik

引用次数: 0

Effect on temperature and time in parallel test scheduling with alterations in layers arrangements of 3D stacked SoCs 三维堆叠soc层序变化对并行测试调度温度和时间的影响

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593029

Indira Rawat, M. K. Gupta, Virendra Singh

{"title":"Effect on temperature and time in parallel test scheduling with alterations in layers arrangements of 3D stacked SoCs","authors":"Indira Rawat, M. K. Gupta, Virendra Singh","doi":"10.1109/VLSI-SATA.2016.7593029","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593029","url":null,"abstract":"In modern electronic complexity, testing of products has become an important area of concern. Low cost and good defect coverage are the basic goals of testing, which are again determined by fault models, test volume and time. Time depends on efficiency of test scheduling scheme. Test scheduling has therefore become an important area of research. Authors have done work on test scheduling and have proposed Test Scheduling Algorithm in previous works done on 3D SoCs. 3D technology fulfils the demand of faster and compact design but there is a sharp rise in power density in such arrangement and therefore there is a sharp rise in temperature especially for the layers far from heat sink. Consequently formation of hotspots may occur which may lead to device failure. Testing dissipates more power than the functional power because of the high switching activity that takes place during testing. All this requires efficient test scheduling so that temperature does not rise above limits. Here temperature and time performance in 3D stacked SoCs with alterations in the arrangement of layers is presented. The modeling of 3D structure is done on HotSpot which is a validated tool widely used in VLSI Testing for temperature determination. The results so obtained are compared with the earlier works of the authors in the same field and an effort is made to draw an inference on temperature rise of cores on account of the variation in placement in 3D SoCs.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115011777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An arbitration on cache replacements based on frequency — Recency product values 基于频率-最近乘积值的缓存替换仲裁

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593031

Somak R. Das, Aikatan Banerjee

引用次数: 4

Tunable distributed harmonic voltage controlled oscillator for generating second and third harmonic microwave signals in 180nm CMOS 用于产生二、三次谐波微波信号的可调谐分布谐波压控振荡器

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593050

K. Bhattacharyya

引用次数: 7

Performance enhancement of slot synchronization in W-CDMA W-CDMA中时隙同步性能的增强

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593051

M. Korde

{"title":"Performance enhancement of slot synchronization in W-CDMA","authors":"M. Korde","doi":"10.1109/VLSI-SATA.2016.7593051","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593051","url":null,"abstract":"The W-CDMA system plays an important role in the 3G cellular systems because of its compatible networking architecture to the present popular Global System for Mobile Communications (GSM) systems as well as the salient features of a Code Division Multiple Access (CDMA) system, including multi-path fading tolerance, high system capacity, low power consumption, good performance and coverage. In CDMA system, a procedure used by a Mobile Station (MS) to search for the best cell site and achieve code, time, and frequency synchronization with it is referred as cell search. Fast cell search is essential to reduce switch on delay (initial cell search), increase stand by time (idle mode search) and maintain good link quality (active-mode search). This is particularly true for the Wideband Code Division Multiple Access-Frequency Division Duplex (W-CDMA-FDD) system since it employs nonsynchronous base stations instead of synchronous ones of other CDMA systems to extend coverage from outdoor to indoor. Cell search is critical for achieving code and time synchronization. The main process of achieving cell search is divided into three stages followed by code verification, tracking and carrier frequency adjustment: 1) slot synchronization, 2) frame synchronization and code group identification, 3) primary scrambling code identification. This paper addresses slot synchronization in downlink as cell search algorithm in W-CDMA. In the three step search, the receiver searches for the slot timing by correlating the received signal with the Primary Synchronization (PSCH) code using Matched Filter (MF). This paper propose a design for a hierarchical matched filter for Primary Synchronization Code (PSC). The aim is to reduce the hardware complexity using Field Programmable Gate Array (FPGA) logic resources required to realize the filter.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129893850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2