2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)最新文献_第3页

Performance of asymmetric gate oxide on gate-drain overlap in Si and Si1−xGex double gate tunnel FETs 非对称栅氧化物对Si和Si1−xGex双栅隧道场效应管栅漏重叠的影响

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593036

S. Poorvasha, B. Lakshmi

引用次数: 1

A RISC-V instruction set processor-micro-architecture design and analysis 一种RISC-V指令集处理器——微体系结构设计与分析

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593047

Aneesh Raveendran, Vinayak Patil, D. Selvakumar, Vivian Desalphine

{"title":"A RISC-V instruction set processor-micro-architecture design and analysis","authors":"Aneesh Raveendran, Vinayak Patil, D. Selvakumar, Vivian Desalphine","doi":"10.1109/VLSI-SATA.2016.7593047","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593047","url":null,"abstract":"Micro-architecture design and analysis of a RISC-V instruction set processor has been articulated in this paper. Instruction Set Architectures (ISAs) for processors from Intel, AMD, Intel, MIPS etc. is protected through IP Rights and Infringements. Few ISAs do exist as open-source viz. Open RISC, SPARC, RISC-V etc. RISC-V ISA has been evolved from the efforts at University of California, Berkeley and has been open sourced as BSD license. This paper details the microarchitecture design and analysis of a 5-stage pipelined RISC-V ISA compatible processor and effects of instruction set on the pipeline / micro-architecture design. The design have been analyzed in terms of instructions encoding, functionality of instructions, instruction types, decoder logic complexity, data hazard detection, register file organization and access, functioning of pipeline, effect of branch instructions, control flow, data memory access, operating modes and execution unit hardware resources. The processor has been micro-architected, simulated using Blue-spec System Verilog, synthesized and analyzed on FPGA platform and 65nm and 130nm technology nodes for ASIC. The synthesis results are compared and analyzed with similar efforts on RISC-V ISA based processor core.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129334386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Automatic pressure maintenance system for tyres in automobiles to reduce accidents 汽车轮胎自动保压系统，减少事故

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593028

R. K. Megalingam, C. Jayakrishnan, Sriraj Nambiar, Rudit Mathews, Vishnu Das, Pramesh Rao

引用次数: 4

Non-intrusive FPGA-based profiler for loop execution characterization 非侵入式基于fpga的循环执行表征分析器

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593046

Pavan Kumar Nadimpalli, S. Roy

引用次数: 0

Reconfigurable side channel attack resistant true random number generator 可重构侧信道攻击抵抗真随机数发生器

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593048

Vijay Bahadur, D. Selvakumar, Vijendran, P. Sobha

{"title":"Reconfigurable side channel attack resistant true random number generator","authors":"Vijay Bahadur, D. Selvakumar, Vijendran, P. Sobha","doi":"10.1109/VLSI-SATA.2016.7593048","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593048","url":null,"abstract":"Random Number Generators (RNGs) play an important role in cryptography. The security of cryptographic algorithms and protocols relies on the ability of RNGs to generate unpredictable secret keys and random numbers. This paper presents an implementation of Side Channel Attack resistant Galois Ring Oscillator (GARO) based True Random Number Generator (TRNG) on FPGA. To study and prove the robustness of the random number generator against placement sensitivity, due to various physical properties of logic elements and thermal variations of FPGA, the design (single instance of GARO) was implemented at four different quadrants in the FPGA and the generated random bit streams were analyzed. Such designs enable resilience against side channel attacks by injection locking. Further, to prove that the implemented TRNG is resilient against side channel attack (Electromagnetic Injection (EM) Attack, Frequency Injection Attack) the frequency spectrum of GARO was captured and analyzed. It was observed that the output of GARO is not dominated by any single frequency unlike non-GARO based ring oscillator which makes it difficult to get locked due to EM / Frequency injection at the specific oscillator frequency. The output bit-stream has been sampled from multiple spatially distributed TRNG units by round-robin. National Institute of Standards and technology (NIST) statistical test suite has been used to benchmark the statistical properties of generated random bit streams and bit streams fulfills all the test suite requirements.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116039350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Design of CMOS programmable output binary and fibonacci switched capacitor step-down DC-DC converter CMOS可编程输出二进制和斐波那契开关电容降压DC-DC变换器的设计

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593034

Mahesh Zanwar, S. Sen

引用次数: 2

Functional verification of DSP based on-board VLSI designs 基于板载VLSI设计的DSP功能验证

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593030

Sourabhkumar Jain, Parimal Govani, Kamal B. Poddar, A. K. Lal, R. Parmar

{"title":"Functional verification of DSP based on-board VLSI designs","authors":"Sourabhkumar Jain, Parimal Govani, Kamal B. Poddar, A. K. Lal, R. Parmar","doi":"10.1109/VLSI-SATA.2016.7593030","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593030","url":null,"abstract":"The Usage of Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASICs) with complex functionalities such as Digital Signal Processing (DSP) is increasing in onboard space applications. Verification of these complex designs within limited schedule and resources is challenging. In order to ensure reliable functioning of these designs in all possible run time conditions, functional verification is required to be carried out thoroughly. Development of an automated self-checking verification environment or test benches, including generation of bit-accurate golden reference values, is complex and time consuming task even with the use of state-of-the-art Hardware Verification Languages (HVLs) and methodology such as System-Verilog (SV) and Universal Verification Methodology (UVM) respectively. This paper discusses a method for functional verification of DSP based VLSI design using SV and Matlab. The architecture of verification environment and technique for coupling of Matlab with SV based verification environment and generation of bitaccurate golden references, in real time is also discussed in detail, along with two case studies.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121212675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Clock skew optimized VLSI architecture for zero frequency filter 零频率滤波器时钟倾斜优化VLSI架构

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593032

K. Radhakrishnan, S. Rani

{"title":"Clock skew optimized VLSI architecture for zero frequency filter","authors":"K. Radhakrishnan, S. Rani","doi":"10.1109/VLSI-SATA.2016.7593032","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593032","url":null,"abstract":"In today's world, mobile phones play an important role in communication. People using mobile phones often face the problem of noise signals affecting the quality of speech. Passive noise control suppresses the higher frequency acoustic noise. It is a technique that provides sound reduction by noise-isolating materials such as insulation, sound-absorbing tiles, or a muffler rather than a power source. In lower frequencies, passive techniques require material that is too bulky and heavy. So an alternative method called active noise cancellation that separates noise signal and speech signal is chosen. Zero frequency filter is a technique used for active noise cancellation of noisy speech signals. This filter is used for the characterization of glottal activity from speech signals thereby cancelling the noise. The main advantage of this method when compared to other noise cancellation methods is that noise need not be modeled separately. In this paper is to present the VLSI implementation architecture of zero frequency filter with useful clock skew optimization. This architecture can be used as voice processor in mobile applications. As clock frequency increases and the technology move towards sub-nanometer process, handling timing violations in the design becomes an increasingly complex and challenging task. Traditional approaches target for global zero skew in the process of timing closure costs in area and power and also limits the maximum achievable operating frequency. Useful clock skew optimization is an emerging technique that helps achieve timing closure. The work presented in this paper achieves timing closure with an area overhead of about 15.87% through useful clock skew optimization.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133542833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A circuit technique for leakage power reduction in CMOS VLSI circuits 一种降低CMOS VLSI电路泄漏功率的电路技术

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593044

Venkata Ramakrishna Nandyala, K. Mahapatra

{"title":"A circuit technique for leakage power reduction in CMOS VLSI circuits","authors":"Venkata Ramakrishna Nandyala, K. Mahapatra","doi":"10.1109/VLSI-SATA.2016.7593044","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593044","url":null,"abstract":"Scaling of CMOS technology improved the speed nevertheless the leakage currents are leftover as an adverse effect. The problem has taken a serious turn as the scaling extends into ultra-deep-submicron (UDSM) region. These unsolicited leakage currents should be minimized for the smooth functioning of the circuit. Designing of such leakage free nanoscale CMOS circuits turns to be a challenging task. In this work, we address the issue of leakage power that arises with the device channel length scaling to sub-100nm. We present a circuit technique to mitigate the leakage currents of MOSFET through controlling the voltage at the source terminal of the MOSFET. CMOS inverter designed using the proposed technique results in 98% and 30% improvement in static and total power dissipation respectively compared with its conventional design. The simulation results of NAND and NOR gates designed using the same technique indicates 15.89% and 18.83% improvement in the total power compared with their corresponding conventional designs. 11-stage CMOS ring oscillator designed using the proposed technique is analyzed, and corresponding simulation results are reported. Comparison of the proposed circuits in terms of power dissipation and delay with two existing techniques is presented. The circuits designed using the proposed technique results in good Power-Delay Product (PDP).","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121168085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

RF tracking test system design for closed loop testing of Ku-band antenna ku波段天线闭环测试射频跟踪测试系统设计

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593049

R. Mishra, Sowbhagya, S. Sudhakar, B. Sudeesh, A. M. Nagalakshmi, S. Udupa

引用次数: 3