Performance of asymmetric gate oxide on gate-drain overlap in Si and Si1−xGex double gate tunnel FETs

Abstract

This paper studies the performance of asymmetric gate oxide on gate-drain overlap for Si and Si_1-xGe_x based double gate (DG) Tunnel FETs (TFETs). For the first time, asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs. For the different values of the mole fraction (x), Si_1-xGe_x is optimized to get ON current (I_ON) enhancement. Si_1-xGe_x based DG TFETs with gate-drain overlap offers a very good I_ON of 232 μA with the subthreshold swing (SS) of 26 mV/dec. This is achieved because of the high tunneling rate of electrons occurring at the source side of Si_1-xGe_x.