{"title":"非对称栅氧化物对Si和Si1−xGex双栅隧道场效应管栅漏重叠的影响","authors":"S. Poorvasha, B. Lakshmi","doi":"10.1109/VLSI-SATA.2016.7593036","DOIUrl":null,"url":null,"abstract":"This paper studies the performance of asymmetric gate oxide on gate-drain overlap for Si and Si<sub>1-x</sub>Ge<sub>x</sub> based double gate (DG) Tunnel FETs (TFETs). For the first time, asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs. For the different values of the mole fraction (x), Si<sub>1-x</sub>Ge<sub>x</sub> is optimized to get ON current (I<sub>ON</sub>) enhancement. Si<sub>1-x</sub>Ge<sub>x</sub> based DG TFETs with gate-drain overlap offers a very good I<sub>ON</sub> of 232 μA with the subthreshold swing (SS) of 26 mV/dec. This is achieved because of the high tunneling rate of electrons occurring at the source side of Si<sub>1-x</sub>Ge<sub>x</sub>.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"66 5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Performance of asymmetric gate oxide on gate-drain overlap in Si and Si1−xGex double gate tunnel FETs\",\"authors\":\"S. Poorvasha, B. Lakshmi\",\"doi\":\"10.1109/VLSI-SATA.2016.7593036\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper studies the performance of asymmetric gate oxide on gate-drain overlap for Si and Si<sub>1-x</sub>Ge<sub>x</sub> based double gate (DG) Tunnel FETs (TFETs). For the first time, asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs. For the different values of the mole fraction (x), Si<sub>1-x</sub>Ge<sub>x</sub> is optimized to get ON current (I<sub>ON</sub>) enhancement. Si<sub>1-x</sub>Ge<sub>x</sub> based DG TFETs with gate-drain overlap offers a very good I<sub>ON</sub> of 232 μA with the subthreshold swing (SS) of 26 mV/dec. This is achieved because of the high tunneling rate of electrons occurring at the source side of Si<sub>1-x</sub>Ge<sub>x</sub>.\",\"PeriodicalId\":328401,\"journal\":{\"name\":\"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)\",\"volume\":\"66 5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-SATA.2016.7593036\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-SATA.2016.7593036","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Performance of asymmetric gate oxide on gate-drain overlap in Si and Si1−xGex double gate tunnel FETs
This paper studies the performance of asymmetric gate oxide on gate-drain overlap for Si and Si1-xGex based double gate (DG) Tunnel FETs (TFETs). For the first time, asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs. For the different values of the mole fraction (x), Si1-xGex is optimized to get ON current (ION) enhancement. Si1-xGex based DG TFETs with gate-drain overlap offers a very good ION of 232 μA with the subthreshold swing (SS) of 26 mV/dec. This is achieved because of the high tunneling rate of electrons occurring at the source side of Si1-xGex.