Functional verification of DSP based on-board VLSI designs

Abstract

The Usage of Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASICs) with complex functionalities such as Digital Signal Processing (DSP) is increasing in onboard space applications. Verification of these complex designs within limited schedule and resources is challenging. In order to ensure reliable functioning of these designs in all possible run time conditions, functional verification is required to be carried out thoroughly. Development of an automated self-checking verification environment or test benches, including generation of bit-accurate golden reference values, is complex and time consuming task even with the use of state-of-the-art Hardware Verification Languages (HVLs) and methodology such as System-Verilog (SV) and Universal Verification Methodology (UVM) respectively. This paper discusses a method for functional verification of DSP based VLSI design using SV and Matlab. The architecture of verification environment and technique for coupling of Matlab with SV based verification environment and generation of bitaccurate golden references, in real time is also discussed in detail, along with two case studies.