2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)最新文献_第4页

Design of 3C-SiC symmetric and asymmetric double gate MOSFET 3C-SiC对称和非对称双栅MOSFET的设计

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593052

Sudarshana Jilowa, S. S. Gill, G. K. Walia

引用次数: 2

Security situational aware intelligent road traffic monitoring using UAVs 使用无人机的安全态势感知智能道路交通监控

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593027

R. Reshma, T. Ramesh, P. Sathishkumar

{"title":"Security situational aware intelligent road traffic monitoring using UAVs","authors":"R. Reshma, T. Ramesh, P. Sathishkumar","doi":"10.1109/VLSI-SATA.2016.7593027","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593027","url":null,"abstract":"Roadway networks span large distances and can be difficult to monitor for managing road traffic. Most efforts to collect usage data from roadways either require a large fixed infrastructure or are labour intensive. Numerous number of road traffic monitoring techniques exists today. Technological advances in electronics and communication have recently enabled an alternative, such as use of Unmanned Aerial Vehicles (UAVs). UAVs are very flexible and fast compared to the normal road traffic monitoring techniques. In addition, security situations can also impact the road traffic management. This paper presents a security situational aware intelligent traffic monitoring using UAV. Such security situational aware road traffic management can also support research and development of intelligent transportation systems (ITS). In this paper, various real time traffic as well as security issues are analysed and mitigations are presented as re-routing of the traffic. The decision commands for re-routing or shortest traffic paths are given by the UAV and these informations are sent to the traffic management control centre. The model was validated using ARM microcontroller simulation using Keil μvision and Proteus tools.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123411451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 44

Design and implementation of reconfigurable coders for communication systems 通信系统可重构编码器的设计与实现

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593063

J. Manikandan, S. Shruthi, S. J. Mangala, V. K. Agrawal

引用次数: 4

OptMem: Dark-silicon aware low latency hybrid memory design OptMem:暗硅感知低延迟混合存储器设计

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593059

S. Onsori, Arghavan Asad, K. Raahemifar, M. Fathy

引用次数: 4

An efficient VLSI architecture for data encryption standard and its FPGA implementation 一种高效的数据加密标准VLSI架构及其FPGA实现

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593054

J. Pandey, Aanchal Gurawa, H. Nehra, A. Karmakar

{"title":"An efficient VLSI architecture for data encryption standard and its FPGA implementation","authors":"J. Pandey, Aanchal Gurawa, H. Nehra, A. Karmakar","doi":"10.1109/VLSI-SATA.2016.7593054","DOIUrl":"https://doi.org/10.1109/VLSI-SATA.2016.7593054","url":null,"abstract":"To achieve the goal of secure communication, cryptography is an essential operation. Many applications, including health-monitoring and biometric data based recognition system, need short-term data security. To design short-term security based applications, there is an essential need of high-performance, low cost and area-efficient VLSI implementation of lightweight ciphers. Data encryption standard (DES) is well-suited for the implementation of low-cost lightweight cryptography applications. In this paper, we propose an efficient VLSI architecture for DES algorithm based encryption/decryption engine. Depending upon the encryption/decryption needs, the same set of architecture performs both encryption and decryption operations. In the implementation of DES algorithm, a chain of multiplexer-based architecture is used to implement the substitution operations (SBoxes). The proposed architecture is modeled in the VHDL design language and synthesized in the Xilinx Virtex-5 xc5vfx70t field-programmable gate array (FPGA) device. Hardware synthesis result shows that the proposed design utilizes only 1.07 % slice LUTs, 0.31 % slice registers and 29.22 % of bonded IOBs of the FPGA device fabric.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134335276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Fully-digital time based ADC/TDC in 0.18μm CMOS 全数字基于时间的ADC/TDC, 0.18μm CMOS

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593040

Vineet R. Sharma, Nupur Jain, B. Mishra

引用次数: 2

A portable platform to estimate power consumption of software modules 一种便携式软件模块功耗估算平台

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593041

A. Bhardwaj, S. Saurav

引用次数: 1

A hierarchical cluster-based model with run-time reconfigurable resource allocation on FPGAs fpga上基于分层簇的运行时可重构资源分配模型

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593053

Amin Yoosefi, H. Naji

引用次数: 1

Implementation of RNS and LNS based addition and subtraction units for cryptography 基于RNS和LNS的密码加减单元的实现

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-SATA.2016.7593055

C. Kumar, A. Prathiba, V. S. Kanchana Bhaskaran

引用次数: 0