Fully-digital time based ADC/TDC in 0.18μm CMOS

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI:10.1109/VLSI-SATA.2016.7593040

Vineet R. Sharma, Nupur Jain, B. Mishra

引用次数: 2

Abstract

This paper proposes a fully digital sensor interface. For this, an analog to digital converter (ADC) and time to digital converter (TDC) based on a common time based ADC (TAD) architecture has been investigated. It is concluded that the proposed fully digital time-based ADC architecture can also be operated as TDC. The fully digital circuit has a ring delay line (RDL), latch, encoder and a synchronous counter. The circuit is implemented in 0.18μm digital CMOS, achieving 139μV/LSB (14-bit, 1-MS/s, 1.6 mW) in ADC mode and 227 ps/LSB (VIN = 1.0 V, 14-bit), 94 ps/LSB (VIN = 1.8 V, 14-bit) in TDC mode respectively. In addition to the scalable design, the resolution of both TDC as well as ADC, can be set by a variable input voltage, VIN.

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全数字基于时间的ADC/TDC, 0.18μm CMOS

本文提出了一种全数字传感器接口。为此，研究了一种基于通用时基ADC (TAD)架构的模数转换器(ADC)和时数转换器(TDC)。结果表明，所提出的全数字基于时间的ADC架构也可以作为TDC工作。全数字电路有环形延迟线(RDL)、锁存器、编码器和同步计数器。该电路采用0.18μm数字CMOS实现，在ADC模式下可实现139μV/LSB(14位，1 ms /s, 1.6 mW)，在TDC模式下可实现227 ps/LSB (VIN = 1.0 V, 14位)，94 ps/LSB (VIN = 1.8 V, 14位)。除了可扩展的设计外，TDC和ADC的分辨率都可以通过可变输入电压VIN来设置。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)

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