Effect on temperature and time in parallel test scheduling with alterations in layers arrangements of 3D stacked SoCs

In modern electronic complexity, testing of products has become an important area of concern. Low cost and good defect coverage are the basic goals of testing, which are again determined by fault models, test volume and time. Time depends on efficiency of test scheduling scheme. Test scheduling has therefore become an important area of research. Authors have done work on test scheduling and have proposed Test Scheduling Algorithm in previous works done on 3D SoCs. 3D technology fulfils the demand of faster and compact design but there is a sharp rise in power density in such arrangement and therefore there is a sharp rise in temperature especially for the layers far from heat sink. Consequently formation of hotspots may occur which may lead to device failure. Testing dissipates more power than the functional power because of the high switching activity that takes place during testing. All this requires efficient test scheduling so that temperature does not rise above limits. Here temperature and time performance in 3D stacked SoCs with alterations in the arrangement of layers is presented. The modeling of 3D structure is done on HotSpot which is a validated tool widely used in VLSI Testing for temperature determination. The results so obtained are compared with the earlier works of the authors in the same field and an effort is made to draw an inference on temperature rise of cores on account of the variation in placement in 3D SoCs.