一种增益增强的CMOS低电压体驱动伪差分OTA设计

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) Pub Date : 1900-01-01 DOI:10.1109/VLSI-SATA.2016.7593045

Antaryami Panigrahi, Abhipsa Parhi

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引用次数: 1

摘要

本文提出了一种0.5V低压体驱动伪差分OTA。在栅极和体电平采用交叉耦合技术来提高OTA磁芯的有效输出电阻。提高了有效输入跨导，实现了高增益。对OTA的运行进行了理论分析，并进行了仿真验证。仿真结果表明，该电路的开环增益为42 dB, UGB为2.3 MHz，相位裕度为85°。当负载为1pF和10kΩ时，输入参考噪声为3.3μV/√Hz，转换率为4.64V/uSec。模拟瞬态响应表明，OTA达到了200mVp-p的满负荷运行。该电路采用250nm双孔CMOS设计，并采用T-Spice和BSIM 3v3模型进行仿真。该OTA的功耗为6.4μWatts。

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A gain enhanced low voltage bulk driven pseudo-differential OTA design in CMOS

A 0.5V low voltage bulk driven pseudodifferential OTA is presented here. Cross coupling technique both at the gate and bulk level is used to increase the effective output resistance of the OTA core. The effective input transconductance is also improved to achieve the high gain. Theoretical analysis for the operation of the OTA is described and simulation is performed to confirm the operation. The simulation results show open loop gain to be 42 dB and UGB of 2.3 MHz and Phase Margin of 85°. The input referred noise is 3.3μV/√Hz, Slew Rate 4.64V/uSec for load of 1pF and 10kΩ. Simulated transient response shows, the OTA achieving full swing of 200mVp-p. The circuit is designed using 250nm twinwell CMOS and simulated using T-Spice and BSIM 3v3 model. The power dissipation of the proposed OTA is 6.4μWatts.

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2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)

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