NEDA based hybrid architecture for DCT — HWT

Transforms are used in many signal processing applications. The VLSI implementation of a hybrid architecture to compute 8-point discrete cosine transform and Haar wavelet transform is proposed. The architecture is developed using NEw Distributed Arithmetic (NEDA) which is an efficient method for implementing inner products without using multipliers and ROM. The architecture developed is coded using Verilog HDL, simulated in ModelSim 6.4 and implemented using Xilinx ISE 14.7. Further, the hybrid architecture is implemented in 0.18μm CMOS technology using Cadence RTL compiler. Compared to standalone architectures, proposed architecture has 77.92% saving in register utilization, 41.80% savings in LUT utilization and 27.55% savings in number of adders used. The results show that the architecture is better in terms of power, hardware resources and complexity compared to earlier architectures.