新型CMOS电流模模糊电路的设计与分析

A. Gubbi, M. Deeksha
{"title":"新型CMOS电流模模糊电路的设计与分析","authors":"A. Gubbi, M. Deeksha","doi":"10.1109/VLSI-SATA.2016.7593035","DOIUrl":null,"url":null,"abstract":"In this paper, the hardware realization of the basic blocks of Fuzzy Inference System (FIS) using simplified inference mechanism circuits are designed and tested in Complementary Metal Oxide Semiconductor (CMOS) Current Mode (CM). These circuits are useful in fuzzy and neuro-fuzzy systems. FIS consists of three main functional blocks. The fuzzification block using Membership Function Generator Circuit (MFGC), rule evaluation and defuzzification. The circuits are designed using the Cadence Virtuoso Design environment in 180nm technology and tested using the Spectre tool. The responses of the circuits, for variations in different signal values are represented using characteristics obtained from spectre tool. The circuit delays and average power are calculated from transient responses with simulation matching the mathematical calculation.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Design and analysis of novel fuzzifer circuits in CMOS current mode approach\",\"authors\":\"A. Gubbi, M. Deeksha\",\"doi\":\"10.1109/VLSI-SATA.2016.7593035\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, the hardware realization of the basic blocks of Fuzzy Inference System (FIS) using simplified inference mechanism circuits are designed and tested in Complementary Metal Oxide Semiconductor (CMOS) Current Mode (CM). These circuits are useful in fuzzy and neuro-fuzzy systems. FIS consists of three main functional blocks. The fuzzification block using Membership Function Generator Circuit (MFGC), rule evaluation and defuzzification. The circuits are designed using the Cadence Virtuoso Design environment in 180nm technology and tested using the Spectre tool. The responses of the circuits, for variations in different signal values are represented using characteristics obtained from spectre tool. The circuit delays and average power are calculated from transient responses with simulation matching the mathematical calculation.\",\"PeriodicalId\":328401,\"journal\":{\"name\":\"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-SATA.2016.7593035\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-SATA.2016.7593035","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

本文利用简化的推理机构电路设计了模糊推理系统基本模块的硬件实现,并在互补金属氧化物半导体(CMOS)电流模式(CM)下进行了测试。这些电路在模糊和神经模糊系统中很有用。FIS由三个主要功能模块组成。模糊化块采用隶属函数产生电路(MFGC)、规则评估和去模糊化。电路使用Cadence Virtuoso Design环境设计,采用180nm技术,并使用Spectre工具进行测试。电路的响应,对不同的信号值的变化是用频谱工具获得的特性表示。根据暂态响应计算电路时延和平均功率,仿真结果与数学计算相吻合。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design and analysis of novel fuzzifer circuits in CMOS current mode approach
In this paper, the hardware realization of the basic blocks of Fuzzy Inference System (FIS) using simplified inference mechanism circuits are designed and tested in Complementary Metal Oxide Semiconductor (CMOS) Current Mode (CM). These circuits are useful in fuzzy and neuro-fuzzy systems. FIS consists of three main functional blocks. The fuzzification block using Membership Function Generator Circuit (MFGC), rule evaluation and defuzzification. The circuits are designed using the Cadence Virtuoso Design environment in 180nm technology and tested using the Spectre tool. The responses of the circuits, for variations in different signal values are represented using characteristics obtained from spectre tool. The circuit delays and average power are calculated from transient responses with simulation matching the mathematical calculation.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信