2020 IEEE 38th VLSI Test Symposium (VTS)最新文献_第4页

Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers 基于网格的可重构封装的TAM线路路由和测试调度协同优化

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/VTS48691.2020.9107604

Jui-Hung Hung, Shih-Hsu Huang, Chun-Hua Cheng, Hsu-Yu Kao, W. Cheng

引用次数: 0

Low-Power Weighted Pseudo-Random Test Pattern Generation for Launch-on-Capture Delay Testing* 低功率加权伪随机测试模式生成的发射捕获延迟测试*

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/VTS48691.2020.9107597

D. Xiang, J. Cai, Bo Liu

引用次数: 3

VTS 2020 Copyright Page VTS 2020版权页面

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/vts48691.2020.9107620

引用次数: 0

LSTM-based Analysis of Temporally- and Spatially-Correlated Signatures for Intermittent Fault Detection 基于lstm的间歇故障时空相关特征分析

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/VTS48691.2020.9107600

Xingyi Wang, Li Jiang, K. Chakrabarty

{"title":"LSTM-based Analysis of Temporally- and Spatially-Correlated Signatures for Intermittent Fault Detection","authors":"Xingyi Wang, Li Jiang, K. Chakrabarty","doi":"10.1109/VTS48691.2020.9107600","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107600","url":null,"abstract":"Intermittent faults are a critical reliability threat in deep submicron VLSI circuits. These faults occur non-deterministically due to unstable hardware and unpredictable operating conditions; they are activated/deactivated with changes in the runtime environment. Online fault prediction models are commonly used to predict soft errors and aging effects. A small set of flip-flops, whose states constitute the signature, conveys information about the fine-grained behavior of the circuit, and serves as the input to a machine-learning (ML) model. The nondeterministic failure mechanisms of intermittent faults, however, result in temporally- and spatially-correlated signatures (TSC-signatures). Moreover, the high-dimensional time-series features impede the use of traditional ML models for intermittent-fault detection. To cope with this challenge, we adapt the TSC-signatures to existing ML detection models. Moreover, we propose a novel detection model based on Recurrent Neural Network with Long Short-Term Memory (LSTM) that is inherently suitable for this problem. Simulation results for the ITC99 benchmark circuits highlight the effectiveness of the proposed model.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128494825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

VTS 2020 Title Page VTS 2020标题页

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/vts48691.2020.9107557

引用次数: 0

Flush+Time: A High Accuracy and High Resolution Cache Attack On ARM-FPGA Embedded SoC Flush+Time:一种基于ARM-FPGA嵌入式SoC的高精度高分辨率缓存攻击

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/VTS48691.2020.9107588

Churan Tang, Pengkun Liu, Cunqing Ma, Zongbin Liu, Jingquan Ge

引用次数: 3

CNN-based Stochastic Regression for IDDQ Outlier Identification 基于cnn的IDDQ离群值识别随机回归

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/VTS48691.2020.9107570

Chun-Teng Chen, Chia-Heng Yen, Cheng Wen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, M. Chao

{"title":"CNN-based Stochastic Regression for IDDQ Outlier Identification","authors":"Chun-Teng Chen, Chia-Heng Yen, Cheng Wen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, M. Chao","doi":"10.1109/VTS48691.2020.9107570","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107570","url":null,"abstract":"In order to reduce DPPM (defect parts per million), IDDQ testing methodology can be exploited for identifying \"outliers\" which are potentially defective but not detected by signoff functional and parametric tests. Conventional IDDQ testing paradigms depending on a simple statistical 6σ rule or engineers’ experience are usually too conservative to effectively identify non-trivial outliers, especially when spatial correlations are of great concern/influence. In this paper, by employing a stochastic regression model, the mean as well as the variance of the IDDQ of a die under test (DUT) can be predicted. According to the predicted mean and variance, we derive an expected IDDQ range and identify the DUT as an outlier if its actual IDDQ measurement is beyond the expected range. The proposed stochastic regression model is obtained by training a convolutional neural network (CNN) and, based on its primitive property of convolutional kernel mapping with large volume of industrial data, spatial correlations (due to spatially-correlated process variations, etc) can be considered/captured. The trained data-driven CNN is highly accurate in terms of R-square (0.958) and RMSE (0.783), and the percentage of identified outliers (0.047%) is very close to the theoretical reference (0.050%), which validates the efficacy of our proposed methodology.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121537005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A New Secure Scan Design with PUF-based Key for Authentication 一种基于puf密钥的安全扫描设计

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/VTS48691.2020.9107566

Qidong Wang, Aijiao Cui, G. Qu, Huawei Li

引用次数: 4

Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits 内置自检多阈值NULL约定逻辑异步电路

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/VTS48691.2020.9107627

Brett Sparkman, S. Smith, J. Di

引用次数: 3

Reliability Evaluation of Turbo Decoders Implemented on SRAM-FPGAs 基于sram - fpga的Turbo译码器可靠性评估

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/VTS48691.2020.9107638

Zhen Gao, Lingling Zhang, Ruishi Han, P. Reviriego, Zhiqiang Li

{"title":"Reliability Evaluation of Turbo Decoders Implemented on SRAM-FPGAs","authors":"Zhen Gao, Lingling Zhang, Ruishi Han, P. Reviriego, Zhiqiang Li","doi":"10.1109/VTS48691.2020.9107638","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107638","url":null,"abstract":"Turbo codes are widely used in satellite communications. When a Turbo decoder is implemented on a Field Programmable Gate Array (FPGA) in a space platform, it will suffer Single Event Upsets (SEUs) that can cause failures and disrupt communications. In this paper, the reliability of Turbo decoders implemented on FPGAs is evaluated. The Turbo decoder with Log-MAP algorithm is implemented on an SRAM-FPGA. Then, fault injection experiments are conducted to simulate the effects of SEU on the user memory and on the configuration memory of the Turbo decoder. Experimental results show that, for user memory, the SEU tolerance rate is over 95%, and the effect of SEU is related to the iteration period, bit position and Signal to Noise Ratio (SNR). In particular, SEUs on the control/address registers and on the interleaving table have a larger impact than on other registers or memories. For the configuration memory, the SEU tolerance rate is higher than 86%, and decreases as SNR increases. In general, the Turbo decoder exhibits a high reliability against SEUs, and the user memory is more reliable than the configuration memory.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123519520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5