2020 IEEE 38th VLSI Test Symposium (VTS)最新文献

Selective Checksum based On-line Error Correction for RRAM based Matrix Operations 基于RRAM矩阵运算的选择性校验和在线纠错

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/VTS48691.2020.9107606

Abhishek Das, N. Touba

{"title":"Selective Checksum based On-line Error Correction for RRAM based Matrix Operations","authors":"Abhishek Das, N. Touba","doi":"10.1109/VTS48691.2020.9107606","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107606","url":null,"abstract":"Resistive RAM technology with it’s in memory computation and matrix vector multiplication capabilities has paved the way for efficient hardware implementations of neural networks. The ability to store the training weights and perform a direct matrix vector multiplication with the applied inputs thus producing the outputs directly reduces a lot of memory transfer overhead. But such schemes are prone to various soft errors and hard errors due to immature fabrication processes creating marginal cells, read disturbance errors, etc. Soft errors are of concern in this case since they can potentially cause mi-classification of objects leading to catastrophic consequences for safety critical applications. Since the location of soft errors are not known previously, they can potentially manifest in the field leading to data corruption. In this paper, a new on-line error correcting scheme is proposed based on partial and selective checksums which can correct errors in the field. The proposed scheme can correct any number of errors in a single column of a given RRAM matrix. Two different checksum computation schemes are proposed, a majority voting-based scheme and a Hamming code-based scheme. The memory overhead and decoding area, latency and dynamic power consumption for both the proposed schemes are presented. It is seen that the proposed solutions can achieve low decoding latency and comparatively smaller memory and area overhead in order to guarantee protection against errors in a single column. Lastly, a scheme to extend the proposed scheme to multiple column errors is also discussed.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122539547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Ultra-Wideband Modulation Signal Measurement Using Local Sweep Digitizing Method 用局部扫描数字化方法测量超宽带调制信号

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/VTS48691.2020.9107610

Koji Asami, Keisuke Kusunoki, N. Shimizu, Yoshiyuki Aoki

引用次数: 2

VTS 2020 Steering and Program Committees VTS 2020指导和项目委员会

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/vts48691.2020.9107596

引用次数: 0

Special Session: Test Challenges in a Chiplet Marketplace 特别会议:芯片市场中的测试挑战

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/VTS48691.2020.9107636

Marc Hutner, R. Sethuram, B. Vinnakota, Dave Armstrong, A. Copperhall

{"title":"Special Session: Test Challenges in a Chiplet Marketplace","authors":"Marc Hutner, R. Sethuram, B. Vinnakota, Dave Armstrong, A. Copperhall","doi":"10.1109/VTS48691.2020.9107636","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107636","url":null,"abstract":"Chiplet-based designs enable the heterogeneous integration of die from multiple process nodes into a single packaged product. High-bandwidth memory is a well-known high-volume chiplet-based product. Today, most chiplet-based logic products are single-vendor products built with proprietary die-to-die (D2D) interfaces between the chiplets in a package. Industry and academia have developed standards and methods to address the test challenges expected with chiplet-based products. These efforts have focused on improving die yield and test access structures. The Open Compute Project’s Open Domain-Specific Architecture (ODSA) is a new effort that aims to define an open physical and logical D2D interface and create a marketplace of chiplets. With an open interface, product developers can integrate best in class chiplets from multiple vendors. An open D2D interface offers both new opportunities and challenges in testing multi-chiplet products. The opportunity is in leveraging economies of scale. The challenge is in enabling greater interoperability between test structures in different chiplets and across vendors. This paper reviews recent developments in chiplet test, especially leveraging work on HBM and discusses their extension to testing products based on open D2D interfaces.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129919281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

SeRFI: Secure Remote FPGA Initialization in an Untrusted Environment SeRFI:在不可信环境中安全远程FPGA初始化

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/VTS48691.2020.9107622

Adam Duncan, Adib Nahiyan, Fahim Rahman, Grant Skipper, D. M. Swany, Andrew Lukefahr, Farimah Farahmandi, M. Tehranipoor

{"title":"SeRFI: Secure Remote FPGA Initialization in an Untrusted Environment","authors":"Adam Duncan, Adib Nahiyan, Fahim Rahman, Grant Skipper, D. M. Swany, Andrew Lukefahr, Farimah Farahmandi, M. Tehranipoor","doi":"10.1109/VTS48691.2020.9107622","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107622","url":null,"abstract":"The bitstream inside a Field-Programmable Gate Array (FPGA) is often protected using an encryption key, acting as a root of trust and stored inside the FPGA, to defend against bitstream piracy, tampering, overproduction, and static-time reverse engineering. For cost savings and faster production, trusted system designers often rely on an untrusted system assembler to program the encryption key into the FPGA, focusing only the end-user-stage threats. However, providing the secret encryption key to an untrusted entity introduces additional threats, since access to this key can compromise the entire root of trust and breach the encrypted bitstream enabling a multitude of attacks including Trojan insertion, piracy and overproduction. To address this issue, we propose the Secure Remote FPGA Initialization (SeRFI) protocol to transmit the encryption key securely from a trusted system designer into an FPGA in physical possession of an untrusted system assembler. Our protocol eliminates direct key sharing with the untrusted system assembler as well as prevents against adversarial intention of extracting the encryption key during the programming phase where the assembler has physical access to the FPGA.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130474091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

[VTS 2020 Awards - 3 Awards] [VTS 2020奖项- 3个奖项]

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/vts48691.2020.9107549

引用次数: 0

A Deterministic-Statistical Multiple-Defect Diagnosis Methodology 一种确定性统计多缺陷诊断方法

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/VTS48691.2020.9107603

Soumya Mittal, R. D. Blanton

引用次数: 0

Switch Level Time Simulation of CMOS Circuits with Adaptive Voltage and Frequency Scaling 具有自适应电压和频率缩放的CMOS电路开关电平时间仿真

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/VTS48691.2020.9107642

E. Schneider, H. Wunderlich

{"title":"Switch Level Time Simulation of CMOS Circuits with Adaptive Voltage and Frequency Scaling","authors":"E. Schneider, H. Wunderlich","doi":"10.1109/VTS48691.2020.9107642","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107642","url":null,"abstract":"Design and test validation of systems with adaptive voltage-and frequency scaling (AVFS) requires timing simulation with accurate timing models under multiple operating points. Such models are usually located at logic level and compromise accuracy and simulation speed due to the runtime complexity.This paper presents the first massively parallel time simulator at switch level that uses parametric delay modeling for efficient timing-accurate validation of systems with AVFS. It provides full glitch-accurate switching activity information of designs under varying supply voltage and temperature. Offline statistical learning with regression analysis is employed to generate polynomials for dynamic delay modeling by approximation of the first-order electrical parameters of CMOS standard cells. With the parallelization on graphics processing units and simultaneous exploitation of multiple dimensions of parallelism the simulation throughput is maximized and scalable-design space exploration of AVFS-based systems is enabled. Results demonstrate the accuracy and efficiency with speedups of up to 159× over conventional logic level time simulation with static delays.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116946946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

[VTS 2020 Title Page] [VTS 2020标题页]

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/vts48691.2020.9107621

引用次数: 0

ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links 在高层通信链路中反向注释的串扰故障模型

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI: 10.1109/VTS48691.2020.9107612

Katayoon Basharkhah, Rezgar Sadeghi, Nooshin Nosrati, Z. Navabi

引用次数: 1