Reliability Evaluation of Turbo Decoders Implemented on SRAM-FPGAs

2020 IEEE 38th VLSI Test Symposium (VTS) Pub Date : 2020-04-01 DOI:10.1109/VTS48691.2020.9107638

Zhen Gao, Lingling Zhang, Ruishi Han, P. Reviriego, Zhiqiang Li

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引用次数: 5

Abstract

Turbo codes are widely used in satellite communications. When a Turbo decoder is implemented on a Field Programmable Gate Array (FPGA) in a space platform, it will suffer Single Event Upsets (SEUs) that can cause failures and disrupt communications. In this paper, the reliability of Turbo decoders implemented on FPGAs is evaluated. The Turbo decoder with Log-MAP algorithm is implemented on an SRAM-FPGA. Then, fault injection experiments are conducted to simulate the effects of SEU on the user memory and on the configuration memory of the Turbo decoder. Experimental results show that, for user memory, the SEU tolerance rate is over 95%, and the effect of SEU is related to the iteration period, bit position and Signal to Noise Ratio (SNR). In particular, SEUs on the control/address registers and on the interleaving table have a larger impact than on other registers or memories. For the configuration memory, the SEU tolerance rate is higher than 86%, and decreases as SNR increases. In general, the Turbo decoder exhibits a high reliability against SEUs, and the user memory is more reliable than the configuration memory.

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基于sram - fpga的Turbo译码器可靠性评估

涡轮码广泛用于卫星通信。当Turbo解码器在空间平台的现场可编程门阵列(FPGA)上实现时，它将遭受单事件干扰(seu)，这可能导致故障并中断通信。本文对基于fpga的Turbo译码器的可靠性进行了评估。采用Log-MAP算法的Turbo解码器在SRAM-FPGA上实现。然后进行故障注入实验，模拟了故障注入对Turbo译码器用户内存和配置内存的影响。实验结果表明，对于用户存储器，SEU容忍率在95%以上，且SEU的效果与迭代周期、比特位置和信噪比有关。特别是，控制/地址寄存器和交错表上的seu比其他寄存器或存储器上的seu影响更大。对于配置内存，SEU容差率大于86%，随信噪比的增加而减小。一般来说，Turbo解码器对seu具有高可靠性，并且用户内存比配置内存更可靠。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2020 IEEE 38th VLSI Test Symposium (VTS)

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