发布求助
文献互助 智能选刊 最新文献

2007 International Symposium on Semiconductor Manufacturing最新文献

筛选
英文 中文
Statistical multi-objective optimization and its application to IC layout design for E-Tests 统计多目标优化及其在电子测试集成电路版图设计中的应用
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446789
Argon Chen, Vic Chen, Chris Hsu
{"title":"Statistical multi-objective optimization and its application to IC layout design for E-Tests","authors":"Argon Chen, Vic Chen, Chris Hsu","doi":"10.1109/ISSM.2007.4446789","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446789","url":null,"abstract":"The ultimate goal of design for manufacturing (DFM) should be a high final yield rather than just a precise reproduction of patterns. To achieve the high yield, this paper is to investigate the effects of the rounding corners, resulting from patterning, on the electrical tests (E-tests) and to determine the optimum layout design such that multiple E-test parameters can attain their desired values simultaneously. Statistical model building and optimization methods are developed and applied to achieve this goal. An actual design layout problem will be used to demonstrate and validate the proposed methods.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122483161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effects of capture rate and its repeatability on optimal sampling requirements in semiconductor manufacturing 半导体制造中捕获率及其可重复性对最佳采样要求的影响
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446897
J. Shanthikumar
{"title":"Effects of capture rate and its repeatability on optimal sampling requirements in semiconductor manufacturing","authors":"J. Shanthikumar","doi":"10.1109/ISSM.2007.4446897","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446897","url":null,"abstract":"We developed a sample planning model for semiconductor manufacturing which incorporates a capture rate model that represents real inspection tool behavior. Current practice is to represent the number of defects caught by an inspection tool by either a binomial random variable or by a fraction of the defects inspected. Models based on these principles merely use the mean capture rate (CR) of the inspection tool to fully characterize the number of defects caught by the inspection tool. The model we developed shows that using only the mean capture rate of the inspection tool does not fully represent the real behavior of the inspection tool. These models completely ignore the second moment properties such as the variance/covariance characteristics of the defect capture process. In this paper we introduce notions of defect-to-defect (DTD), wafer-to-wafer (WTW)and lot-to-lot (LTL) capture rate repeatability that represent the variance/covariance characteristics of the defect capture process in our sample planning model. Our study based on this model shows that the false alarm rate and lots at risk for a given sample plan depend heavily on the capture rate repeatability. Furthermore, the optimal sample plan for a given risk tolerance can be influenced substantially by this repeatability. In this paper we present a new sample planner model that incorporates capture rate repeatability. We define the necessary notions of capture rate repeatability and use them to develop the sample planner model. We present the risk trade-offs, and an algorithm to compute the optimal sample plan for a pre-specified risk level. Finally, we present the numerical results and our analysis of their implications.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124223047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Implementation of double patterning lithography process using limited illumination systems 采用有限照明系统的双图案光刻工艺的实现
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446858
C. Choi, Miller Qiu, W. Li, H. Sui, F. Mieno
{"title":"Implementation of double patterning lithography process using limited illumination systems","authors":"C. Choi, Miller Qiu, W. Li, H. Sui, F. Mieno","doi":"10.1109/ISSM.2007.4446858","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446858","url":null,"abstract":"The double patterning (DP) process is mainly for the resolution enhancement beyond limited lithography system not only high numerical aperture (NA) system but small one also. In this paper, we developed several duty patterns using DP technology under ArF, 0.75 NA systems to meet the 65 nm half-pitch patterns. For the line DP process, it is clear that the limited resolution is 65 nm half pitch pattern with marginal process windows and overlay should be controlled within 30 nm, M+3 sigma value. For the 2nd patterning process, there is dose shift compared with Is patterning dose for the substrate difference. From these results, DP technologies can be applied to overcome resolution limited process not only fine patterning required but certain patterning which can be achieved without any investments.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127291058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Photo track defect control using multiple masking layer defect data 利用多掩蔽层缺陷数据控制照片轨迹缺陷
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446845
T. Couteau, A. Gutierrez, P. Dye
{"title":"Photo track defect control using multiple masking layer defect data","authors":"T. Couteau, A. Gutierrez, P. Dye","doi":"10.1109/ISSM.2007.4446845","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446845","url":null,"abstract":"The defect monitoring strategy presented here has been developed for defectivity feedback for track and stepper issues typically seen in a high volume multi-device manufacturing facility. It combines data streams from multiple masking layers and product mixes improving the signal to noise ratio (S/N) of the defectivity signal utilizing an AMD/Spansion developed statistical control system known as ASPECT. True defect driven failures at the current layer, faster feedback loops, and a more comprehensive look at potential problems within the photo lithography area are the results of this integrated monitor process control strategy.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133193503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An approach of dynamic bottleneck machine dispatching for semiconductor wafer fab 半导体晶圆厂动态瓶颈机器调度方法
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446814
Zhang Huai, J. Zhibin, Lee Yen-Fei, Ko Chen-Pin, L. Choo Ooi Tuck, Lim Lee Phing
{"title":"An approach of dynamic bottleneck machine dispatching for semiconductor wafer fab","authors":"Zhang Huai, J. Zhibin, Lee Yen-Fei, Ko Chen-Pin, L. Choo Ooi Tuck, Lim Lee Phing","doi":"10.1109/ISSM.2007.4446814","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446814","url":null,"abstract":"This paper proposed a dynamic bottleneck dispatching (DBD) policy to consider the dynamic bottlenecks for semiconductor wafer fabrication system. The DBD policy adopted the multi-class priority queuing model and developed a procedure to assign lots to different priority classes. Each queuing lot was assigned to a priority class by 3 decision parameters, which could be optimized by the response surface method and a desirability function approach. A case study based on a local fab was described to examine the performance impact of the DBD policy measured by CT, Var CT, WIP, and TP. The results of the simulation experiments and analysis showed that the DBD policy is superior to the use of the static dispatching rules. In future work, the DBD policy could be integrated with manufacturing execution system (MES) for scheduling wafer fab.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127622711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Virtual metrology for plasma particle in plasma etching equipment 等离子体蚀刻设备中等离子体粒子的虚拟测量
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446835
S. Imai
{"title":"Virtual metrology for plasma particle in plasma etching equipment","authors":"S. Imai","doi":"10.1109/ISSM.2007.4446835","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446835","url":null,"abstract":"Virtual metrology for a plasma particle in plasma etching equipment is described in this paper for the first time. No direct measurement of plasma particles is carried out by an inspection tool but the generation of plasma particles can be predicted by detecting plasma density change indirectly measured using an equipment monitoring tool. It is found that the plasma density change can be detected by several equipment parameters like self-bias voltage using PLS analysis. The correlation coefficient of 0.75 is obtained between measured number of particles and predicted number of particles by a virtual parameter. It is demonstrated that the virtual parameter generated several parameters is useful as virtual metrology for a plasma particle.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"104 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131279237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Using design based binning to improve defect excursion control for 45nm production 采用基于设计的分形技术改进45nm工艺的缺陷偏移控制
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446790
C. Huang, C. Young, H. Liu, S. F. Tzou, D. Tsui, A. Tsai, E. Chang
{"title":"Using design based binning to improve defect excursion control for 45nm production","authors":"C. Huang, C. Young, H. Liu, S. F. Tzou, D. Tsui, A. Tsai, E. Chang","doi":"10.1109/ISSM.2007.4446790","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446790","url":null,"abstract":"For advanced device (45 nm and below), we proposed a novel method to monitor systematic and random excursion. By integrating design information and defect inspection results into automated software (DBB), we can identify design/process marginality sites with defect inspection tool. In this study, we applied supervised binning function (DBC) and defect criticality index (DCI) to identify systematic and random excursion problems on 45 nm SRAM wafers. With established SPC charts, we will be able to detect future excursion problem in manufacturing line early.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124312681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Improving direct labour productivity through minimizing time wastage approach 通过减少时间浪费来提高直接劳动生产率
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446822
Wai Kuan Cheong, Soon Onn Look, H. Mohamed
{"title":"Improving direct labour productivity through minimizing time wastage approach","authors":"Wai Kuan Cheong, Soon Onn Look, H. Mohamed","doi":"10.1109/ISSM.2007.4446822","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446822","url":null,"abstract":"As today, most IC supplies are still from 200 mm fab. When most 200 mm fab completed the tool depreciation cycle, the ratio of human cost in total wafer cost increased. The human productivity improvement would further improve wafer fabrication cost reduction. Compared to 300 mm fab, a 200 mm fab is more labour intensive in that human intervention is required. Hence, direct labour productivity may be impacted by non-value added tasks that are associated with the routine activities of an operator. In this paper, we take the unconventional way of improving labour productivity by minimizing time wastages caused by non-value added activities. This study with improvement action focuses on time wastage in queuing for metrology tools and handling of control wafers. By creating usage schedule of metrology tools across the fabs, and having dispatching rules for highly utilized metrology tools, this study aims to reduce waiting time in front of metrology tools and thereby improving direct labour productivity and improving a certain level of fab OEE.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126144098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimize die size design to enhance owe for design for manufacturing 优化模具尺寸设计，提高生产设计效率
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446788
Chen-Fu Chien, Chia-Chih Liu, Chia-Yu Hsu, Hong-Shing Chou, Chih-Wei Lin
{"title":"Optimize die size design to enhance owe for design for manufacturing","authors":"Chen-Fu Chien, Chia-Chih Liu, Chia-Yu Hsu, Hong-Shing Chou, Chih-Wei Lin","doi":"10.1109/ISSM.2007.4446788","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446788","url":null,"abstract":"To enhance competitive advantages, it is crucial for wafer fabs to reduce average die cost through productivity improvement via increasing the number of gross dies per wafer and throughput. However, gross die number is influenced by die size in design phase, while the existing size of integrated circuit die was designed without considering the effect on wafer throughput in fabrication phase. This research aims to develop a die size optimization algorithm based on decision tree to construct the rules between the number of gross dies per wafer, mask utilization, and the die feature including length, width, and area. Without losing generality, an empirical study has been done for validation by using transformed data from a fab in Taiwan.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126226428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Extending HDP for STI fill to 45nm with IPM 使用IPM将STI填充的HDP扩展到45nm
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446868
Anchuan Wang, J. Bloking, Linlin Wang, Manoj Vellaikal, Jin Ho Jeon, Young S. Lee, Harry S Whitesell
{"title":"Extending HDP for STI fill to 45nm with IPM","authors":"Anchuan Wang, J. Bloking, Linlin Wang, Manoj Vellaikal, Jin Ho Jeon, Young S. Lee, Harry S Whitesell","doi":"10.1109/ISSM.2007.4446868","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446868","url":null,"abstract":"A novel gap fill approach, Integrated Profile Modulation (IPM), with repeating deposition and etch cycles is developed to extend HDP for complete gap fill to 45 nm node and beyond, with established HDP CVD film properties and integration. In this paper, the key aspects of the IPM process, deposition, etch, in-film fluorine and aluminum control are discussed to provide better understanding on gap fill optimization and manufacturing capability.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127687053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
首页 上一页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信