Effects of capture rate and its repeatability on optimal sampling requirements in semiconductor manufacturing

Abstract

We developed a sample planning model for semiconductor manufacturing which incorporates a capture rate model that represents real inspection tool behavior. Current practice is to represent the number of defects caught by an inspection tool by either a binomial random variable or by a fraction of the defects inspected. Models based on these principles merely use the mean capture rate (CR) of the inspection tool to fully characterize the number of defects caught by the inspection tool. The model we developed shows that using only the mean capture rate of the inspection tool does not fully represent the real behavior of the inspection tool. These models completely ignore the second moment properties such as the variance/covariance characteristics of the defect capture process. In this paper we introduce notions of defect-to-defect (DTD), wafer-to-wafer (WTW)and lot-to-lot (LTL) capture rate repeatability that represent the variance/covariance characteristics of the defect capture process in our sample planning model. Our study based on this model shows that the false alarm rate and lots at risk for a given sample plan depend heavily on the capture rate repeatability. Furthermore, the optimal sample plan for a given risk tolerance can be influenced substantially by this repeatability. In this paper we present a new sample planner model that incorporates capture rate repeatability. We define the necessary notions of capture rate repeatability and use them to develop the sample planner model. We present the risk trade-offs, and an algorithm to compute the optimal sample plan for a pre-specified risk level. Finally, we present the numerical results and our analysis of their implications.