Optimize die size design to enhance owe for design for manufacturing

Abstract

To enhance competitive advantages, it is crucial for wafer fabs to reduce average die cost through productivity improvement via increasing the number of gross dies per wafer and throughput. However, gross die number is influenced by die size in design phase, while the existing size of integrated circuit die was designed without considering the effect on wafer throughput in fabrication phase. This research aims to develop a die size optimization algorithm based on decision tree to construct the rules between the number of gross dies per wafer, mask utilization, and the die feature including length, width, and area. Without losing generality, an empirical study has been done for validation by using transformed data from a fab in Taiwan.