2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)最新文献_第4页

An event-driven simulation methodology for integrated switching power supplies in SystemVerilog SystemVerilog中集成开关电源的事件驱动仿真方法

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488903

Jieun Jang, Myeong-Jae Park, Jaeha Kim

{"title":"An event-driven simulation methodology for integrated switching power supplies in SystemVerilog","authors":"Jieun Jang, Myeong-Jae Park, Jaeha Kim","doi":"10.1145/2463209.2488903","DOIUrl":"https://doi.org/10.1145/2463209.2488903","url":null,"abstract":"Emerging power-supply-on-chip applications such as on-chip DCDC conversion, energy harvesting, and LED drivers use switching regulator ICs integrated with digital controllers. Although the resulting mixed-signal systems call for efficient system-level behavioral simulation, this remains difficult due to the fast switching and slow transients of the regulator and the high complexity of the controller. This paper presents a truly event-driven approach for modeling and simulating such integrated power systems entirely in SystemVerilog. By modeling various switching regulator topologies as switched linear networks whose responses can be expressed as a sum of complex exponentials, ctm-1e-atu(t), the accurate voltage/current waveforms can be captured by updating the coefficients, c, at each input or switching event. The model is applied to two examples, a power factor corrector and switched-capacitor DC-DC converter, and the results demonstrate that the proposed simulator can achieve 20~100× improvements in speed while maintaining SPICE-level accuracy in evaluating power efficiency, steady-state ripples, and power factor.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130441289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

A heterogeneous multiple network-on-chip design: An application-aware approach 异构多片上网络设计:一种应用感知方法

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488779

Asit K. Mishra, O. Mutlu, C. Das

{"title":"A heterogeneous multiple network-on-chip design: An application-aware approach","authors":"Asit K. Mishra, O. Mutlu, C. Das","doi":"10.1145/2463209.2488779","DOIUrl":"https://doi.org/10.1145/2463209.2488779","url":null,"abstract":"Current network-on-chip designs in chip-multiprocessors are agnostic to application requirements and hence are provisioned for the general case, leading to wasted energy and performance. We observe that applications can generally be classified as either network bandwidth-sensitive or latency-sensitive. We propose the use of two separate networks on chip, where one network is optimized for bandwidth and the other for latency, and the steering of applications to the appropriate network. We further observe that not all bandwidth (latency) sensitive applications are equally sensitive to network bandwidth (latency). Hence, within each network, we prioritize packets based on the relative sensitivity of the applications they belong to. We introduce two metrics, network episode height and length, as proxies to estimate bandwidth and latency sensitivity, to classify and rank applications. Our evaluations show that the resulting heterogeneous two-network design can provide significant energy savings and performance improvements across a variety of workloads compared to a single one-size-fits-all single network and homogeneous multiple networks.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129265143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 79

Throughput-oriented kernel porting onto FPGAs 面向吞吐量的内核移植到fpga上

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488747

Alexandros Papakonstantinou, Deming Chen, Wen-mei W. Hwu, J. Cong, Yun Liang

引用次数: 9

System architecture and software design for Electric Vehicles 电动汽车系统架构与软件设计

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488852

M. Lukasiewycz, S. Steinhorst, Sidharta Andalam, Florian Sagstetter, Peter Waszecki, Wanli Chang, M. Kauer, Philipp Mundhenk, Shanker Shreejith, Suhaib A. Fahmy, S. Chakraborty

{"title":"System architecture and software design for Electric Vehicles","authors":"M. Lukasiewycz, S. Steinhorst, Sidharta Andalam, Florian Sagstetter, Peter Waszecki, Wanli Chang, M. Kauer, Philipp Mundhenk, Shanker Shreejith, Suhaib A. Fahmy, S. Chakraborty","doi":"10.1145/2463209.2488852","DOIUrl":"https://doi.org/10.1145/2463209.2488852","url":null,"abstract":"This paper gives an overview of the system architecture and software design challenges for Electric Vehicles (EVs). First, we introduce the EV-specific components and their control, considering the battery, electric motor, and electric powertrain. Moreover, technologies that will help to advance safety and energy efficiency of EVs such as drive-by-wire and information systems are discussed. Regarding the system architecture, we present challenges in the domain of communication and computation platforms. A paradigm shift towards time-triggered in-vehicle communication systems becomes inevitable for the sake of determinism, making the introduction of new bus systems and protocols necessary. At the same time, novel computational devices promise high processing power at low cost which will make a reduction in the number of Electronic Control Units (ECUs) possible. As a result, the software design has to be performed in a holistic manner, considering the controlled component while transparently abstracting the underlying hardware architecture. For this purpose, we show how middleware and verification techniques can help to reduce the design and test complexity. At the same time, with the growing connectivity of EVs, security has to become a major design objective, considering possible threats and a security-aware design as discussed in this paper.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126825400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 45

Dynamic behavior of cell signaling networks - Model design and analysis automation 细胞信号网络的动态行为。模型设计和分析自动化

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488743

Nataša Miškov-Živanov, Diana Marculescu, J. Faeder

引用次数: 12

A direct finite element solver of linear complexity for large-scale 3-D circuit extraction in multiple dielectrics 多介质中大规模三维电路提取的线性复杂性直接有限元求解器

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488906

Bangda Zhou, Haixin Liu, D. Jiao

引用次数: 7

XDRA: Exploration and optimization of last-level cache for energy reduction in DDR DRAMs XDRA: DDR dram中降低能耗的最后一级缓存的探索与优化

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488761

S. Min, Haris Javaid, S. Parameswaran

{"title":"XDRA: Exploration and optimization of last-level cache for energy reduction in DDR DRAMs","authors":"S. Min, Haris Javaid, S. Parameswaran","doi":"10.1145/2463209.2488761","DOIUrl":"https://doi.org/10.1145/2463209.2488761","url":null,"abstract":"Embedded systems with high energy consumption often exploit the idleness of DDR-DRAM to reduce their energy consumption by putting the DRAM into deepest low-power mode (self-refresh power down mode) during idle periods. DDR-DRAM idle periods heavily depend on the last-level cache. Exhaustive search using processor-memory simulators can take several months. This paper for first time proposes a fast framework called XDRA, which allows the exploration of last-level cache configurations to improve DDR-DRAM energy efficiency. XDRA combines a processor-memory simulator, a cache simulator and novel analysis techniques to produce a Kriging based estimator which predicts the energy savings for differing cache configurations for a given main memory size and application. Errors for the estimator were less than 4.4% on average for 11 applications from mediabench and SPEC2000 suite and two DRAM sizes (Micron DDR3-DRAM 256MB and 4GB). Cache configurations selected by XDRA were on average 3.6× and 4× more energy efficient (cache and DRAM energy) than a common cache configuration. Optimal cache configurations were selected by XDRA 20 times out of 22. The two suboptimal configurations were at most 3.9% from their optimal counterparts. XDRA took a few days for the exploration of 330 cache configurations compared to several hundred days of cycle-accurate simulations, saving at least 85% of exploration time.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132918687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Tessellation: Refactoring the OS around explicit resource containers with continuous adaptation 镶嵌:围绕显式资源容器重构操作系统，并不断进行调整

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488827

Juan A. Colmenares, Gage Eads, S. Hofmeyr, Sarah Bird, Miquel Moretó, David Chou, Brian Gluzman, Eric Roman, D. Bartolini, Nitesh Mor, K. Asanović, J. Kubiatowicz

引用次数: 65

Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs 三维集成电路中全片多TSV-to-TSV耦合提取与优化

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488956

Taigon Song, Chang Liu, Yarui Peng, S. Lim

引用次数: 33

VeriTrust: Verification for hardware trust VeriTrust:硬件信任验证

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488808

Jie Zhang, F. Yuan, Lingxiao Wei, Zelong Sun, Q. Xu

引用次数: 209