2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)最新文献

An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem 一种解决时钟偏差变化问题的可调延迟缓冲器插入优化算法

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488845

Juyeon Kim, Deokjin Joo, Taewhan Kim

{"title":"An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem","authors":"Juyeon Kim, Deokjin Joo, Taewhan Kim","doi":"10.1145/2463209.2488845","DOIUrl":"https://doi.org/10.1145/2463209.2488845","url":null,"abstract":"Meeting clock skew constraint is one of the most important tasks in the synthesis of clock trees. Moreover, the problem becomes much hard to tackle as the delay of clock signals varies dynamically during execution. Recently, it is shown that adjustable delay buffer (ADB) whose delay can be adjusted dynamically can solve the clock skew variation problem effectively. However, inserting ADBs requires non-negligible area and control overhead. Thus, all previous works have invariably aimed at minimizing the number of ADBs to be inserted, particularly under the environment of multiple power modes in which the operating voltage applied to some modules varies as the power mode changes. In this work, unlike the previous works which have solved the ADB minimization problem heuristically or locally optimally, we propose an elegant and easily adoptable solution to overcome the limitation of the previous works. Precisely, we propose an O(n log n) time (bottom-up traversal) algorithm that (1) optimally solves the problem of minimizing the number of ADBs to be inserted with continuous delay of ADBs and (2) enables solving the ADB insertion problem with discrete delay of ADBs to be greatly simple and predictable. In addition, we propose (3) a systematic solution to an important extension to the problem of buffer sizing combined with the ADB insertion to further reduce the ADBs to be used.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115706370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 34

An efficient layout decomposition approach for Triple Patterning Lithography 一种高效的三模光刻版面分解方法

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488818

Jian Kuang, Evangeline F. Y. Young

引用次数: 96

Design of cyberphysical digital microfluidic biochips under completion-time uncertainties in fluidic operations 流体作业完井时间不确定性下的数字微流控生物芯片设计

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488788

Yan Luo, K. Chakrabarty, Tsung-Yi Ho

{"title":"Design of cyberphysical digital microfluidic biochips under completion-time uncertainties in fluidic operations","authors":"Yan Luo, K. Chakrabarty, Tsung-Yi Ho","doi":"10.1145/2463209.2488788","DOIUrl":"https://doi.org/10.1145/2463209.2488788","url":null,"abstract":"Cyberphysical digital microfluidics enables the integration of fluid-handling operations, reaction-outcome detection, and software-based control in a biochip. However, synthesis algorithms and biochip design methods proposed in the literature are oblivious to completion-time uncertainties in fluidic operations, and they do not meet the requirements of cyberphysical integration in digital microfluidics. We present an operation-interdependency-aware synthesis method that uses frequency scaling and is responsive to uncertainties that are inherent in the completion times of fluidic operations such as mixing and thermal cycling. Using this design approach, we can carry out dynamic on-line decision making for the execution of fluidic operations in response to detector feedback. We use three common laboratorial protocols to demonstrate that, compared to uncertainty-oblivious biochip design, the proposed dynamic decision making approach is more effective in satisfying realistic physical constraints. As a result, it decreases the likelihood of erroneous reaction outcomes, and it leads to reduced time-to-results, less repetition of reaction steps, and less wastage of precious samples and reagents.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127540388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Liveness evaluation of a Cyclo-Static DataFlow Graph 循环静态数据流图的活动性评价

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488736

M. Benazouz, Alix Munier Kordon, Thomas Hujsa, Bruno Bodin

引用次数: 12

A robust constraint solving framework for multiple constraint sets in Constrained Random Verification 约束随机验证中多约束集的鲁棒约束求解框架

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488880

Bo-Han Wu, Chung-Yang Huang

引用次数: 3

Reconfigurable pipelined coprocessor for multi-mode communication transmission 用于多模式通信传输的可重构流水线协处理器

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488899

L. Tang, Jude Angelo Ambrose, S. Parameswaran

{"title":"Reconfigurable pipelined coprocessor for multi-mode communication transmission","authors":"L. Tang, Jude Angelo Ambrose, S. Parameswaran","doi":"10.1145/2463209.2488899","DOIUrl":"https://doi.org/10.1145/2463209.2488899","url":null,"abstract":"The need to integrate multiple wireless communication protocols into a single low-cost, low-power hardware platform is prompted by the increasing number of emerging communication protocols and applications. This paper presents a novel application specific platform for integrating multiple wireless communication transmission baseband protocols in a pipelined coprocessor, which can be programmed to support various baseband protocols. This coprocessor can dynamically select the suitable pipeline stages for each baseband protocol. Moreover, each carefully designed stage is able to perform a certain signal processing function in a reconfigurable fashion. The proposed platform is flexible (compared to ASICs) and is suitable for mobile applications (compared to FPGAs and processors). The area footprint of the coprocessor is smaller than an ASIC or FPGA implementation of multiple individual protocols, while the overhead of throughput is 34% worse than ASICs and 32% better than FPGAs. The power consumption is 2.7X worse than ASICs but 40X better than FPGAs on average. The proposed platform outperforms processor implementation in all area, throughput and power consumption. Moreover, fast protocol switching is supported. Wireless LAN (WLAN) 802.11 a, WLAN 802.11 b and Ultra Wide Band (UWB) transmission circuits are developed and mapped to the pipelined coprocessor to prove the efficacy of our proposal.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128354595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Modular system-level architecture for concurrent cell balancing 用于并行单元平衡的模块化系统级架构

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488926

M. Kauer, Swaminathan Naranayaswami, S. Steinhorst, M. Lukasiewycz, S. Chakraborty, L. Hedrich

引用次数: 24

Non-volatile FPGAs based on spintronic devices 基于自旋电子器件的非易失性fpga

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488889

O. Goncalves, G. Prenat, G. D. Pendina, B. Dieny

引用次数: 17

Taming the complexity of coordinated place and route 控制地点和路线协调的复杂性

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488920

Jin Hu, Myung-Chul Kim, I. Markov

引用次数: 18

Stochastic response-time guarantee for non-preemptive, fixed-priority scheduling under errors 错误下非抢占、固定优先级调度的随机响应时间保证

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488946

Philip Axer, R. Ernst

引用次数: 17