用于多模式通信传输的可重构流水线协处理器

L. Tang, Jude Angelo Ambrose, S. Parameswaran
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引用次数: 7

摘要

越来越多的新兴通信协议和应用促使人们需要将多种无线通信协议集成到一个低成本、低功耗的硬件平台中。本文提出了一种将多种无线通信传输基带协议集成到一个流水线协处理器中的专用平台,该平台可编程支持多种基带协议。该协处理器可以动态地为每个基带协议选择合适的管道阶段。此外,每个精心设计的阶段都能够以可重构的方式执行特定的信号处理功能。所提出的平台是灵活的(与asic相比),并适用于移动应用(与fpga和处理器相比)。协处理器的面积占用比多个单独协议的ASIC或FPGA实现要小,而吞吐量开销比ASIC低34%,比FPGA高32%。功耗比asic低2.7倍,但平均比fpga好40倍。该平台在所有领域、吞吐量和功耗方面都优于处理器实现。支持快速协议交换。开发了无线局域网(WLAN) 802.11 a、WLAN 802.11 b和超宽带(UWB)传输电路,并将其映射到流水线协处理器上,以证明我们的建议的有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Reconfigurable pipelined coprocessor for multi-mode communication transmission
The need to integrate multiple wireless communication protocols into a single low-cost, low-power hardware platform is prompted by the increasing number of emerging communication protocols and applications. This paper presents a novel application specific platform for integrating multiple wireless communication transmission baseband protocols in a pipelined coprocessor, which can be programmed to support various baseband protocols. This coprocessor can dynamically select the suitable pipeline stages for each baseband protocol. Moreover, each carefully designed stage is able to perform a certain signal processing function in a reconfigurable fashion. The proposed platform is flexible (compared to ASICs) and is suitable for mobile applications (compared to FPGAs and processors). The area footprint of the coprocessor is smaller than an ASIC or FPGA implementation of multiple individual protocols, while the overhead of throughput is 34% worse than ASICs and 32% better than FPGAs. The power consumption is 2.7X worse than ASICs but 40X better than FPGAs on average. The proposed platform outperforms processor implementation in all area, throughput and power consumption. Moreover, fast protocol switching is supported. Wireless LAN (WLAN) 802.11 a, WLAN 802.11 b and Ultra Wide Band (UWB) transmission circuits are developed and mapped to the pipelined coprocessor to prove the efficacy of our proposal.
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