XDRA: Exploration and optimization of last-level cache for energy reduction in DDR DRAMs

Abstract

Embedded systems with high energy consumption often exploit the idleness of DDR-DRAM to reduce their energy consumption by putting the DRAM into deepest low-power mode (self-refresh power down mode) during idle periods. DDR-DRAM idle periods heavily depend on the last-level cache. Exhaustive search using processor-memory simulators can take several months. This paper for first time proposes a fast framework called XDRA, which allows the exploration of last-level cache configurations to improve DDR-DRAM energy efficiency. XDRA combines a processor-memory simulator, a cache simulator and novel analysis techniques to produce a Kriging based estimator which predicts the energy savings for differing cache configurations for a given main memory size and application. Errors for the estimator were less than 4.4% on average for 11 applications from mediabench and SPEC2000 suite and two DRAM sizes (Micron DDR3-DRAM 256MB and 4GB). Cache configurations selected by XDRA were on average 3.6× and 4× more energy efficient (cache and DRAM energy) than a common cache configuration. Optimal cache configurations were selected by XDRA 20 times out of 22. The two suboptimal configurations were at most 3.9% from their optimal counterparts. XDRA took a few days for the exploration of 330 cache configurations compared to several hundred days of cycle-accurate simulations, saving at least 85% of exploration time.