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2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)最新文献

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Improving the energy efficiency of hardware-assisted watchpoint systems 提高硬件辅助观察点系统的能源效率
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488800
Vasileios Karakostas, Sasa Tomic, O. Unsal, M. Nemirovsky, A. Cristal
{"title":"Improving the energy efficiency of hardware-assisted watchpoint systems","authors":"Vasileios Karakostas, Sasa Tomic, O. Unsal, M. Nemirovsky, A. Cristal","doi":"10.1145/2463209.2488800","DOIUrl":"https://doi.org/10.1145/2463209.2488800","url":null,"abstract":"Hardware-assisted watchpoint systems enhance the execution of numerous dynamic software techniques, such as memory protection, module isolation, deterministic execution, and data race detection. In this paper, we show that previous hardware proposals may introduce significant energy overheads, and propose WatchPoint Filtering (WPF), a novel filtering mechanism that eliminates unnecessary watchpoint checks. We evaluate WPF on two state-of-the-art proposals for hardware-assisted watchpoints using two common memory checkers. WPF eliminates 83% of the watchpoint checks (up to 99.7%) and reduces 57% of the dynamic energy overhead (up to 78%) on average, without introducing additional performance execution overhead.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"316 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115375329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique 传输门物理不可克隆功能和片上电压-数字转换技术
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488806
Rajdeep Chakraborty, Charles Lamech, D. Acharyya, J. Plusquellic
{"title":"A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique","authors":"Rajdeep Chakraborty, Charles Lamech, D. Acharyya, J. Plusquellic","doi":"10.1145/2463209.2488806","DOIUrl":"https://doi.org/10.1145/2463209.2488806","url":null,"abstract":"A physical unclonable function (PUF) is an embedded integrated circuit (IC) structure that is designed to leverage naturally occurring variations to produce a random bitstring. In this paper, we evaluate a PUF which leverages resistance variations which occur in transmission gates (TGs) of ICs. We also investigate a novel on-chip technique for converting the voltage drops produced by TGs into a digital code, i.e., a voltage-to-digital converter (VDC). The analysis is carried out on data measured from chips subjected to temperature variations over the range of -40°C to +85°C and voltage variations of +/- 10% of the nominal supply voltage. The TG PUF and VDC produce high quality bitstrings that perform exceptionally well under statistical metrics including stability, randomness and uniqueness.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114759327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Bayesian Model Fusion: Large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data 贝叶斯模型融合:通过重用早期数据对模拟和混合信号电路进行大规模性能建模
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488812
Fa Wang, Paolo Cachecho, Wangyang Zhang, Shupeng Sun, Xin Li, R. Kanj, Chenjie Gu
{"title":"Bayesian Model Fusion: Large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data","authors":"Fa Wang, Paolo Cachecho, Wangyang Zhang, Shupeng Sun, Xin Li, R. Kanj, Chenjie Gu","doi":"10.1145/2463209.2488812","DOIUrl":"https://doi.org/10.1145/2463209.2488812","url":null,"abstract":"Efficient high-dimensional performance modeling of today's complex analog and mixed-signal (AMS) circuits with large-scale process variations is an important yet challenging task. In this paper, we propose a novel performance modeling algorithm that is referred to as Bayesian Model Fusion (BMF). Our key idea is to borrow the simulation data generated from an early stage (e.g., schematic level) to facilitate efficient high-dimensional performance modeling at a late stage (e.g., post layout) with low computational cost. Such a goal is achieved by statistically modeling the performance correlation between early and late stages through Bayesian inference. Several circuit examples designed in a commercial 32nm CMOS process demonstrate that BMF achieves up to 9× runtime speedup over the traditional modeling technique without surrendering any accuracy.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117298991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 89
Single-photon image sensors 单光子图像传感器
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488891
E. Charbon, F. Regazzoni
{"title":"Single-photon image sensors","authors":"E. Charbon, F. Regazzoni","doi":"10.1145/2463209.2488891","DOIUrl":"https://doi.org/10.1145/2463209.2488891","url":null,"abstract":"The main goal of this paper is to expose the EDA community to the emerging class of circuits operating with single quanta of energy (e.g. photons or electrical carriers). We describe recent developments in the field of single-photon detection and single-photon imaging based on the avalanche effect. Single-photon detection is useful in a number of applications, from time-of-flight based 3D vision systems to fluorescence lifetime imaging microscopy, from low-light cameras to quantum random number generators, from positron emission tomography to time-resolved Raman spectroscopy. These applications have speed and accuracy requirements that conventional systems cannot provide if not at a very high cost. EDA has not yet adapted to the revolution introduced by avalanching devices and, though tools capable of simulating these devices exist, there is little or no capability to do so in a coherent flow, let alone at system level. We challenge CAD designers to fill this gap and prepare them to the circuits of the future, quantum in nature but built in standard CMOS technology.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116356751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Exploiting just-enough parallelism when mapping streaming applications in hard real-time systems 在硬实时系统中映射流应用程序时，利用刚好足够的并行性
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488944
J. Zhai, M. Bamakhrama, T. Stefanov
{"title":"Exploiting just-enough parallelism when mapping streaming applications in hard real-time systems","authors":"J. Zhai, M. Bamakhrama, T. Stefanov","doi":"10.1145/2463209.2488944","DOIUrl":"https://doi.org/10.1145/2463209.2488944","url":null,"abstract":"Embedded streaming applications specified using parallel Models of Computation (MoC) often contain ample amount of parallelism which can be exploited using Multi-Processor System-on-Chip (MPSoC) platforms. It has been shown that the various forms of parallelism in an application should be explored to achieve the maximum system performance. However, if more parallelism is revealed than needed, it will overload the underlying MPSoC platform. At the same time, the revealed parallelism should be sufficient such that the MPSoC platform is fully utilized. Therefore, the amount of revealed and exploited parallelism has to be just-enough with respect to the platform constraints. In this paper, we study the problem of exploiting just-enough parallelism by application task unfolding, when mapping streaming applications modeled using the Synchronous Data Flow (SDF) MoC onto MPSoC platforms in hard real-time systems. We show that our problem of simultaneously unfolding and allocating tasks under hard real-time scheduling has a bounded solution space and derive its upper bounds. Subsequently, we devise an efficient algorithm to solve the problem, while the obtained solution meets a pre-specified quality. The experiments on a set of real-life streaming applications demonstrate that our algorithm results, within reasonable amount of time, in a system specification with large performance gain. Finally, we show that our proposed algorithm is on average 100 times faster than one of the state-of-the-art meta-heuristics, i.e., NSGA-II genetic algorithm, while achieving the same quality of solutions.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123221574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
FPGA code accelerators - The compiler perspective FPGA代码加速器-编译器视角
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488908
W. Najjar, J. Villarreal
{"title":"FPGA code accelerators - The compiler perspective","authors":"W. Najjar, J. Villarreal","doi":"10.1145/2463209.2488908","DOIUrl":"https://doi.org/10.1145/2463209.2488908","url":null,"abstract":"FPGA-based accelerators have repeatedly demonstrated superior speed-ups on an ever-widening spectrum of applications. However, their use remains beyond the reach of traditionally trained applications code developers because of the complexity of their programming tool-chain. Compilers for high-level languages targeting FPGAs have to bridge a huge abstraction gap between two divergent computational models: a temporal, sequentially consistent, control driven execution in the stored program model versus a spatial, parallel, data-flow driven execution in the spatial hardware model. In this paper we discuss these challenges to the compiler designer and report on our experience with the ROCCC toolset.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129759922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
On learning-based methods for design-space exploration with High-Level Synthesis 基于学习的高层次综合设计空间探索方法研究
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488795
Hung-Yi Liu, L. Carloni
{"title":"On learning-based methods for design-space exploration with High-Level Synthesis","authors":"Hung-Yi Liu, L. Carloni","doi":"10.1145/2463209.2488795","DOIUrl":"https://doi.org/10.1145/2463209.2488795","url":null,"abstract":"This paper makes several contributions to address the challenge of supervising HLS tools for design space exploration (DSE). We present a study on the application of learning-based methods for the DSE problem, and propose a learning model for HLS that is superior to the best models described in the literature. In order to speedup the convergence of the DSE process, we leverage transductive experimental design, a technique that we introduce for the first time to the CAD community. Finally, we consider a practical variant of the DSE problem, and present a solution based on randomized selection with strong theory guarantee.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128324368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 180
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints 基于寿命和误差约束的能量优化SRAM供电电压调度
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488870
A. Calimera, E. Macii, M. Poncino
{"title":"Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints","authors":"A. Calimera, E. Macii, M. Poncino","doi":"10.1145/2463209.2488870","DOIUrl":"https://doi.org/10.1145/2463209.2488870","url":null,"abstract":"This work addresses the energy efficiency of the memory architecture in safety-critical systems that have to guarantee a given level of service and a minimum lifetime. We specifically target SRAM structures in which decreased reliability manifests itself in terms of the aging induced by NBTI (Negative Bias Temperature Instability), and in which the level of service is represented by the bit-error rate (BER). Our approach is based on the idea of determining an energy-optimal scheduling of supply voltages for the SRAM that satisfy the specified lifetime and BER constraints. The construction of the scheduling leverages semi-empirical models for the quantity of interest (aging, energy, memory performance, error rate) in terms of the supply voltage, and is determined through a search-based algorithm in the corresponding solution space. The optimization framework is embedded into a design space exploration tool that allows browsing the energy/performance/ reliability space for the various desired lifetime/error rate and by varying architectural parameters such operating frequency and memory size.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127161897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Improving energy gains of inexact DSP hardware through reciprocative error compensation 通过往复误差补偿提高不精确DSP硬件的能量增益
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488759
L. Avinash, A. Basu, C. Enz, K. Palem, C. Piguet
{"title":"Improving energy gains of inexact DSP hardware through reciprocative error compensation","authors":"L. Avinash, A. Basu, C. Enz, K. Palem, C. Piguet","doi":"10.1145/2463209.2488759","DOIUrl":"https://doi.org/10.1145/2463209.2488759","url":null,"abstract":"We present a zero hardware-overhead design approach called reciprocative error compensation(REC) that significantly enhances the energy-accuracy trade-off gains in inexact signal processing datapaths by using a two-pronged approach: (a) deliberately redesigning the basic arithmetic blocks to effectively compensate for each other's (expected) error through inexact logic minimization, and (b) “reshaping” the response waveforms of the systems being designed to further reduce any residual error. We apply REC to several DSP primitives such as the FFT and FIR filter blocks, and show that this approach delivers 2-3 orders of magnitude lower (expected) error and more than an order of magnitude lesser Signal-to-Noise Ratio (SNR) loss (in dB) over the previously proposed inexact design techniques, while yielding similar energy gains. Post-layout comparisons in the 65nm process technology show that our REC approach achieves upto 73% energy savings (with corresponding delay and area savings of upto 16% and 62% respectively) when compared to an existing exact DSP implementation while trading a relatively small loss in SNR of less than 1.5 dB.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127173676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
An optimized page translation for mobile virtualization 为移动虚拟化优化的页面翻译
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488838
Yuan-Cheng Lee, Chih-wen Hsueh
{"title":"An optimized page translation for mobile virtualization","authors":"Yuan-Cheng Lee, Chih-wen Hsueh","doi":"10.1145/2463209.2488838","DOIUrl":"https://doi.org/10.1145/2463209.2488838","url":null,"abstract":"Recently, the significant progress in embedded microprocessors made it practical to support virtualization on mobile devices. Unfortunately, memory management has not been well studied in consideration of the characteristics of mobile virtualization due to the challenging aspects on both hardware and software. With a formal proof on a novel design of page translation at the second stage, we propose a novel design of page translation on both hardware and software with higher translation speed, lower variance of latency, and lower hardware complexity. The experimental results suggest it can reduce memory access by 51.37% to 56.01% as compared with the traditional approach.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128904706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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