{"title":"An optimized page translation for mobile virtualization","authors":"Yuan-Cheng Lee, Chih-wen Hsueh","doi":"10.1145/2463209.2488838","DOIUrl":null,"url":null,"abstract":"Recently, the significant progress in embedded microprocessors made it practical to support virtualization on mobile devices. Unfortunately, memory management has not been well studied in consideration of the characteristics of mobile virtualization due to the challenging aspects on both hardware and software. With a formal proof on a novel design of page translation at the second stage, we propose a novel design of page translation on both hardware and software with higher translation speed, lower variance of latency, and lower hardware complexity. The experimental results suggest it can reduce memory access by 51.37% to 56.01% as compared with the traditional approach.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2463209.2488838","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
Recently, the significant progress in embedded microprocessors made it practical to support virtualization on mobile devices. Unfortunately, memory management has not been well studied in consideration of the characteristics of mobile virtualization due to the challenging aspects on both hardware and software. With a formal proof on a novel design of page translation at the second stage, we propose a novel design of page translation on both hardware and software with higher translation speed, lower variance of latency, and lower hardware complexity. The experimental results suggest it can reduce memory access by 51.37% to 56.01% as compared with the traditional approach.