Shaofeng Guo, Ru Huang, P. Hao, Mulong Luo, P. Ren, Jianping Wang, Weihai Bu, Jingang Wu, W. Wong, Scott Yu, Hanming Wu, Shiuh-Wuu Lee, Runsheng Wang, Yangyuan Wang
{"title":"DTMOS mode as an effective solution of RTN suppression for robust device/circuit co-design","authors":"Shaofeng Guo, Ru Huang, P. Hao, Mulong Luo, P. Ren, Jianping Wang, Weihai Bu, Jingang Wu, W. Wong, Scott Yu, Hanming Wu, Shiuh-Wuu Lee, Runsheng Wang, Yangyuan Wang","doi":"10.1109/IEDM.2014.7047040","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047040","url":null,"abstract":"In this paper, using DTMOS as an effective solution of RTN suppression without device/circuit performance penalty is proposed and demonstrated for the first time, with experimental verification and circuit analysis. The experiments show that RTN amplitude is greatly reduced in DTMOS mode, which is even better than the body-biasing technique of FBB, due to the efficient dynamic modulation mechanism. Circuit stability and performance degradation induced by RTN are much improved in the design using DTMOS. New characteristics of RTN physics in DTMOS are also observed and studied in detail. The results are helpful to the robust and reliable device/circuit co-design in future nano-CMOS technology.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133542691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Desalvo, P. Morin, M. Pala, G. Ghibaudo, O. Rozeau, Q. Liu, A. Pofelski, S. Martini, M. Cassé, S. Pilorget, F. Allibert, F. Chafik, T. Poiroux, P. Scheer, R. Southwick, D. Chanemougame, L. Grenouillet, K. Cheng, F. Andrieu, S. Barraud, S. Maitrejean, E. Augendre, H. Kothari, N. Loubet, W. Kleemeier, M. Celik, O. Faynot, M. Vinet, R. Sampson, B. Doris
{"title":"A mobility enhancement strategy for sub-14nm power-efficient FDSOI technologies","authors":"B. Desalvo, P. Morin, M. Pala, G. Ghibaudo, O. Rozeau, Q. Liu, A. Pofelski, S. Martini, M. Cassé, S. Pilorget, F. Allibert, F. Chafik, T. Poiroux, P. Scheer, R. Southwick, D. Chanemougame, L. Grenouillet, K. Cheng, F. Andrieu, S. Barraud, S. Maitrejean, E. Augendre, H. Kothari, N. Loubet, W. Kleemeier, M. Celik, O. Faynot, M. Vinet, R. Sampson, B. Doris","doi":"10.1109/IEDM.2014.7047002","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047002","url":null,"abstract":"Continuous CMOS improvement has been achieved in recent years through strain engineering for mobility enhancement. Nevertheless, as transistor pitch is scaled down, conventional strain elements (as embedded stressors, stress liners) are loosing their effectiveness [1]. The use of strained materials for the channel to boost performance is thus essential. In this paper, we present an original multilevel evaluation methodology for stress engineering design in next-generation power-efficient devices. Fully-Depleted-Silicon-On-Insulator (FDSOI) is chosen as the ideal test vehicle, as it offers the advantage of sustaining significant stress within the channel without plastic relaxation (the thin channel staying below the critical thickness [2]). Starting from 3D mechanical simulations and piezoresistive coefficient data, an original, simple, physically-based model for holes/electrons mobility enhancement in strained devices is developed. The model is calibrated on physical measurements and electrical data of state-of-the-art devices. Non-Equilibrium Greens Function (NEGF) quantum simulations of holes/electrons stress-enhanced mobility give physical insights into mobility behavior at large stress (~3GPa). Finally, the new strained-enhanced mobility model is introduced in an industrial compact model [3] to project evaluation at the circuit level.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133683997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Can piezoelectricity lead to negative capacitance?","authors":"Justin C. Wong, S. Salahuddin","doi":"10.1109/IEDM.2014.7047046","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047046","url":null,"abstract":"A thermodynamic model was constructed to quantitatively analyze the negative capacitance effect in the presence of piezoelectricity, electrostriction, and ferroelectricity. The model shows that pure piezoelectricity and higher-order electromechanical coupling can provide a negative capacitance effect in principle, but are not strong enough in practice. Negative capacitance is predicted to occur due to ferroelectric polarization switching and not due to piezoelectricity.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133146434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Meneghesso, M. Meneghini, A. Chini, G. Verzellesi, E. Zanoni
{"title":"Trapping and high field related issues in GaN power HEMTs","authors":"G. Meneghesso, M. Meneghini, A. Chini, G. Verzellesi, E. Zanoni","doi":"10.1109/IEDM.2014.7047072","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047072","url":null,"abstract":"Gallium Nitride HEMTs grown on Si substrates are the most promising solution for the future technologies in the power electronics industry. Compensation of unintentional GaN n-type conductivity is specifically mandatory in the buffer for an optimum device blocking function. Carbon (C) or Iron (Fe) doping are the most common solutions that however are responsible also for the introduction of traps in the buffer, that induce large charge trapping and current collapse when devices are biased at high voltages as well as affect breakdown behavior of these devices. This paper reviews the main high field related issues recently reported in GaN-on-Si devices for power applications.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116216231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Huang, Q. Jiang, K. Wei, G. Liu, X. Wang, Y. Zheng, B. Sun, C. Zhao, H. Liu, Z. Jin, X. Liu, H. Wang, S. Liu, Y. Lu, C. Liu, S. Yang, Z. Tang, J. Zhang, Y. Hao, K. J. Chen
{"title":"High-temperature low-damage gate recess technique and ozone-assisted ALD-grown Al2O3 gate dielectric for high-performance normally-off GaN MIS-HEMTs","authors":"S. Huang, Q. Jiang, K. Wei, G. Liu, X. Wang, Y. Zheng, B. Sun, C. Zhao, H. Liu, Z. Jin, X. Liu, H. Wang, S. Liu, Y. Lu, C. Liu, S. Yang, Z. Tang, J. Zhang, Y. Hao, K. J. Chen","doi":"10.1109/IEDM.2014.7047071","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047071","url":null,"abstract":"A high-temperature (180 °C) gate recess technique featuring low damage and in-situ self-clean capability, in combination with O<sub>3</sub>-assisted atomic-layer-deposition (ALD) of Al<sub>2</sub>O<sub>3</sub> gate dielectric, is developed for fabrication of high performance normally-off AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs), which exhibit a threshold voltage of +1.6 V, a pulsed drive current of 1.1 A/mm, and low dynamic ON-resistance under hard-switching operation. Chlorine-based dry-etching residues (e.g. AlCl<sub>3</sub> and GaCl<sub>3</sub>) are significantly reduced by increasing the wafer temperature during the gate recess to their characteristic desorption temperature, while defective bonds like Al-O-H and positive fixed charges in ALD-Al<sub>2</sub>O<sub>3</sub> are significantly suppressed by substitution of H<sub>2</sub>O with O<sub>3</sub> precursor.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"33 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116481425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Ikeda, H. Sato, H. Honjo, E. C. Enobio, S. Ishikawa, M. Yamanouchi, S. Fukami, S. Kanai, F. Matsukura, T. Endoh, H. Ohno
{"title":"Perpendicular-anisotropy CoFeB-MgO based magnetic tunnel junctions scaling down to 1X nm","authors":"S. Ikeda, H. Sato, H. Honjo, E. C. Enobio, S. Ishikawa, M. Yamanouchi, S. Fukami, S. Kanai, F. Matsukura, T. Endoh, H. Ohno","doi":"10.1109/IEDM.2014.7047160","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047160","url":null,"abstract":"CoFeB-MgO based magnetic tunnel junction with perpendicular easy axis (p-MTJ) shows a high potential to be used in spintronics based very large scale integrated circuits and spin-transfer-torque magnetorestive random access memories. In this paper, we review development of p-MTJ using single CoFeB-MgO and double CoFeB-MgO interface structures. The TMR ratio shows 164% after annealing at 400 °C, indicating the CoFeB-MgO p-MTJs have capability for back-end-of-line. Scaling properties of p-MTJs using double CoFeB-MgO interface structure are also reviewed.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114741976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I-Ting Wang, Yen-Chuan Lin, Yu-Fen Wang, Chung-Wei Hsu, T. Hou
{"title":"3D synaptic architecture with ultralow sub-10 fJ energy per spike for neuromorphic computation","authors":"I-Ting Wang, Yen-Chuan Lin, Yu-Fen Wang, Chung-Wei Hsu, T. Hou","doi":"10.1109/IEDM.2014.7047127","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047127","url":null,"abstract":"A high-density 3D synaptic architecture based on self-rectifying Ta/TaOx/TiO2/Ti RRAM is proposed as an energy- and cost-efficient neuromorphic computation hardware. The device shows excellent analog synaptic features that can be accurately described by the physical and compact models. Ultra-low energy consumption comparable to that of a biological synapse (<;10 fJ/spike) has been demonstrated for the first time.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132293634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Howell, E. Stewart, R. Freitag, J. Parke, B. Nechay, H. Cramer, M. King, Shalini Gupta, J. Hartman, M. Snook, I. Wathuthanthri, Parrish Ralston, K. Renaldo, H. G. Henry, R. C. Clarke
{"title":"The Super-Lattice Castellated Field Effect Transistor (SLCFET): A novel high performance Transistor topology ideal for RF switching","authors":"R. Howell, E. Stewart, R. Freitag, J. Parke, B. Nechay, H. Cramer, M. King, Shalini Gupta, J. Hartman, M. Snook, I. Wathuthanthri, Parrish Ralston, K. Renaldo, H. G. Henry, R. C. Clarke","doi":"10.1109/IEDM.2014.7047033","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047033","url":null,"abstract":"NGES reports the development of a novel transistor structure based on a GaN super-lattice channel with a 3D gate, named the SLCFET (Super-Lattice Castellated Field Effect Transistor). Transistor measurements provided median values of I<sub>MAX</sub>>2.7 A/mm, V<sub>PINCH</sub> = -8V, with R<sub>ON</sub>=0.41 Ω-mm and C<sub>OFF</sub>=0.19 pF/mm, for an RF switch FOM of F<sub>CO</sub>=2.1 THz.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133498363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Ji, Martin D. McDaniel, L. Tao, Xiaohang Li, A. Posadas, Yao‐Feng Chang, A. Demkov, J. Ekerdt, D. Akinwande, R. Ruoff, Jack C. Lee, E. Yu
{"title":"Atomic scale engineering of metal-oxide-semiconductor photoelectrodes for energy harvesting application integrated with Graphene and Epitaxy SrTiO3","authors":"L. Ji, Martin D. McDaniel, L. Tao, Xiaohang Li, A. Posadas, Yao‐Feng Chang, A. Demkov, J. Ekerdt, D. Akinwande, R. Ruoff, Jack C. Lee, E. Yu","doi":"10.1109/IEDM.2014.7047013","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047013","url":null,"abstract":"In this work, hydrogen production from water is demonstrated via a p-type silicon photocathode with a thin epitaxial strontium titanate, SrTiO3 (STO), as capping layer by molecular beam epitaxy. The advantages of using STO are the ideal conduction band alignment and perfect lattice match between single crystalline SrTiO3 and Si, so the photogenerated electrons can transport through the capping layer with a reduced recombination rate. The STO/p-Si photocathode exhibited a maximum photocurrent density and open circuit potential of 35 mA/cm2 and 450 mV, respectively. There was no observable decrease in performance after 10 hr operation in 0.5M H2SO4. We found the efficiency and performance were highly dependent on the size and spacing of the structured metal catalyst. Scaled down the metal catalysts feature size into nanometer region can greatly improve the efficiency. In addition, samples with graphene (Grahene/p-Si) as the lateral transport channel and capping layer shown an enhanced fill factor compared with that of STO/p-Si.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126986610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Kothandaraman, S. Cohen, C. Parks, J. Golz, K. Tunga, S. Rosenblatt, J. Safran, C. Collins, W. Landers, J. Oakley, J. Liu, A. Martin, K. Petrarca, M. Farooq, T. Graves-abe, N. Robson, S. Iyer
{"title":"Through silicon via (TSV) effects on devices in close proximity - the role of mobile ion penetration - characterization and mitigation","authors":"C. Kothandaraman, S. Cohen, C. Parks, J. Golz, K. Tunga, S. Rosenblatt, J. Safran, C. Collins, W. Landers, J. Oakley, J. Liu, A. Martin, K. Petrarca, M. Farooq, T. Graves-abe, N. Robson, S. Iyer","doi":"10.1109/IEDM.2014.7047053","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047053","url":null,"abstract":"A new interaction between TSV processes and devices in close proximity, different from mechanical stress, is identified, studied and mitigated. Detailed characterization via Triangular Voltage Sweep (TVS) and SIMS shows the role of mobile ion penetration from BEOL layers. An improved process is presented and confirmed in test structures and DRAM.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"82 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121925751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}