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Initial FPGA design for generalized Orthogonal Nonsinusoidal Division Multiplexing 广义正交非正弦分复用的FPGA初步设计
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397813
P. Misans, G. Valters
{"title":"Initial FPGA design for generalized Orthogonal Nonsinusoidal Division Multiplexing","authors":"P. Misans, G. Valters","doi":"10.1109/NORCHP.2009.5397813","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397813","url":null,"abstract":"Generalized Orthogonal Nonsinusoidal Division Multiplexing (GONDM) is a novel multicarrier modulation technique and a promising alternative to the well established OFDM and the wavelet based OWDM. Complex CRAIMOT (CCRAIMOT) transform is used in GONDM, as an alternative of conventional IFFT/FFT. Simplified digital parts of GONDM transmitter and receiver have been implemented into Altera's FPGA. Hardware tests of simplified GONDM with AWGN channel in the baseband have been performed. Bit error rate (BER) performances of OFDM and GONDM for different rotation angles and QPSK mapping are compared. Preliminary results show that GONDM is a promising modulation technique for the building of adaptive data transmission systems.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127445457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Measurement of a timing error detection latch capable of sub-threshold operation 能够进行亚阈值操作的定时误差检测锁存器的测量
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397791
M. Turnquist, E. Laulainen, Jani Makipaa, M. Pulkkinen, L. Koskinen
{"title":"Measurement of a timing error detection latch capable of sub-threshold operation","authors":"M. Turnquist, E. Laulainen, Jani Makipaa, M. Pulkkinen, L. Koskinen","doi":"10.1109/NORCHP.2009.5397791","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397791","url":null,"abstract":"To take advantage of minimum energy consumption in sub-threshold, systems are required to have robustness to variability. In sub-threshold, exponential drain current dependence on the threshold voltage produces large sensitivities to variations. Adaptive systems are required to respond to these conditions. One adaptive method, called timing error detection (TED), eliminates traditional safety margins by scaling the supply voltage or frequency until timing errors. Presented here is a TED latch test circuit that makes use of sub-threshold operation. The circuit was fabricated with a 65 nm CMOS process, operates from 0.2V to 1.2V, and has a minimum energy point (MEP) near 0.2V. Using a testing matrix of voltage and frequency pairs, the error rate and energy per operation were also measured.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"2009 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125626993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A reconfigurable SoC tailored to Software Defined Radio applications 为软件定义无线电应用量身定制的可重构SoC
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397829
F. Garzia, Waqar Hussain, Roberto Airoldi, J. Nurmi
{"title":"A reconfigurable SoC tailored to Software Defined Radio applications","authors":"F. Garzia, Waqar Hussain, Roberto Airoldi, J. Nurmi","doi":"10.1109/NORCHP.2009.5397829","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397829","url":null,"abstract":"This paper presents the mapping of SDR applications on a reconfigurable SoC, based on a run-time reconfigurable coarse-grain accelerator called CREMA. CREMA is characterized by mapping adaptiveness, meaning that its architecture is specified according to the needs of the application mapped on it. CREMA is used to accelerate two kernels used in SDR applications: correlations for synchronization purposes and FFT for the OFDM modulation/demodulation. In both cases we show that the implementation on CREMA is 4X faster that a similar implementation on a general-purpose coarse-grain accelerator, and that its resource occupation is reduced by 4.5X.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"325 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115701535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Physical design and reliability issues in nanoscale analog CMOS technologies 纳米级模拟CMOS技术的物理设计和可靠性问题
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397862
L. Lewyn
{"title":"Physical design and reliability issues in nanoscale analog CMOS technologies","authors":"L. Lewyn","doi":"10.1109/NORCHP.2009.5397862","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397862","url":null,"abstract":"In nanoscale analog CMOS design there is no good substitute for understanding reliability stress factors or the many effects related to the circuit physical layout which can cause significant design-for-reliability (DFR), performance (DFP), or manufacturability (DFM) yield degradation. Circuit simulation tools presently lack the capability to predict the effect of several stress and reliability effects, including TDDB, HCI, NBTI, etc. Physical design deficiencies found after post-layout-extraction result in re-layout and a waste of the industries most valuable commodity: time to market. This paper presents an overview of these effects on nanoscale analog circuit design and also explores how to alter device geometries to mitigate them. Additionally, methods for extending device terminal voltage limits under certain conditions beyond foundry-specified voltage limits will be explored.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114335348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Near-optimum switched capacitor sample-and-hold circuit 近乎最佳的开关电容取样保持电路
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397857
F. Centurelli, A. Simonetti, A. Trifiletti
{"title":"Near-optimum switched capacitor sample-and-hold circuit","authors":"F. Centurelli, A. Simonetti, A. Trifiletti","doi":"10.1109/NORCHP.2009.5397857","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397857","url":null,"abstract":"Performance of the low-voltage and power-efficient analog-to-digital (A/D) converters, like cyclic and pipeline topologies, can be significantly enhanced by using advanced analog cores. This paper describes a careful switched capacitor (SC) architecture that can be used as a simple low-voltage implementation of the flip-around sample-and-hold (S/H) circuit. The S/H has been simulated in a 0.13µm CMOS technology featuring a signal to noise and distortion ratio (SNDR) of −75dB at 12Ms/s for a 1Vpp output voltage. Theoretical calculations and experimental results are also given to demonstrate its validity.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122200487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A practical FPGA-based LUT-predistortion technology for switch-mode power amplifier linearization 一种实用的基于fpga的开关模式功率放大器线性化的lut预失真技术
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397830
U. Cerasani, Y. Le Moullec, T. Tong
{"title":"A practical FPGA-based LUT-predistortion technology for switch-mode power amplifier linearization","authors":"U. Cerasani, Y. Le Moullec, T. Tong","doi":"10.1109/NORCHP.2009.5397830","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397830","url":null,"abstract":"In the context of wireless communications, power amplifiers raise a number of issues. Mastering the linearity vs. efficiency trade-off is not trivial. Switch-mode power amplifiers can provide high power efficiency. However, they exhibit significant nonlinearities, which make them difficult to apply in modern high linear modulation wireless systems. In order to enable their use in such systems, a LUT-based predistortion technique targeting switch-mode PA linearization is introduced. Particularly the predistortion function derivation for handling the whole input interval of the nonlinearity predistortion is described. A 0.18µm CMOS Class F power amplifier is used as the study-case for testing and evaluating the proposed approach. Matlab and DSP-Builder blocks targeting a Stratix II FPGA simulation results show that the proposed LUT-based predistortion technique effectively improves the linearity of the switch-mode PA with an average EVM of less than 2%.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130310938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
UWB Vivaldi antenna for impulse radio beamforming 脉冲无线电波束形成的超宽带维瓦尔第天线
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397796
Tuan-Anh Vu, M. Z. Dooghabadi, S. Sudalaiyandi, H. A. Hjortland, O. Naess, T. Lande, S. Hamran
{"title":"UWB Vivaldi antenna for impulse radio beamforming","authors":"Tuan-Anh Vu, M. Z. Dooghabadi, S. Sudalaiyandi, H. A. Hjortland, O. Naess, T. Lande, S. Hamran","doi":"10.1109/NORCHP.2009.5397796","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397796","url":null,"abstract":"In this paper, two different types of Vivaldi antenna are designed and tested suitable for electromagnetic beamforming. The first is an antipodal Vivaldi antenna, while the other is a tapered slot Vivaldi antenna. They are both ultra wideband antennas for the 1 GHz to 5 GHz frequency band. They have low impulse distortion and the voltage standing wave ratio (VSWR) less than 2 throughout the entire bandwidth. The antennas are used for impulse radio beamforming.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"1025 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134214380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A 2–5 Gb/s fully differential 3X oversampling CDR for high-speed serial data link 用于高速串行数据链路的2 - 5gb /s全差分3X过采样CDR
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397815
Nathan Kiddinapillai, T. Kwasniewski
{"title":"A 2–5 Gb/s fully differential 3X oversampling CDR for high-speed serial data link","authors":"Nathan Kiddinapillai, T. Kwasniewski","doi":"10.1109/NORCHP.2009.5397815","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397815","url":null,"abstract":"This paper presents the design and implementation of a fully differential 3X oversampling clock and data recovery (CDR) circuit for high-speed serial data link. The CDR is capable of operating at any speed from 2 to 5 Gb/s. The architecture of the CDR replaces the analog VCO and loop filter used in analog PLL based CDR with digital circuits. The CDR uses a digital threshold decision technique to improve the jitter tolerance performance. System level simulation shows that the CDR has a high frequency jitter tolerance of 0.67 UI and acquisition time of 8 baud period. The CDR is implemented in 65 nm CMOS process technology. The post-layout simulation is performed for 27–1 PRBS data. The CDR consumes 39 mW from 1.1 V power supply at 5 Gb/s. The core CDR circuit occupies an area of 0.013mm2.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134580198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Inverter-based 1V transimpedance amplifier in 90nm CMOS for medical ultrasound imaging 基于逆变器的90纳米CMOS 1V跨阻放大器用于医学超声成像
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397856
Linga Reddy Cenkeramaddi, T. Singh, T. Ytterdal
{"title":"Inverter-based 1V transimpedance amplifier in 90nm CMOS for medical ultrasound imaging","authors":"Linga Reddy Cenkeramaddi, T. Singh, T. Ytterdal","doi":"10.1109/NORCHP.2009.5397856","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397856","url":null,"abstract":"In this paper, we propose a 1V transimpedance amplifier design based on an inverter based cascode amplifier as opposed to the conventional transimpedance amplifier based on an Operational Transconductance Amplifier (OTA). The proposed amplifier is designed to amplify the signals from Capacitive Micro machined Ultrasound Transducers (CMUTs) in the frequency bandwidth from 15MHz to 45MHz with a center frequency of 30MHz for medical ultrasound imaging systems. From the measurements, the proposed single-ended transimpedance amplifier achieves a voltage gain of 18.9 dB, an output noise power spectral density of 0.0421 (µV)/SQRT(Hz) at a center-frequency of 30 MHz, and a total harmonic distortion of −23.16 dB, at 450mV p-p output voltage at 30 MHz input signal frequency. It draws only 598 µA current per amplifier from a 1-V power supply. The proposed single-ended trans-impedance amplifier was fabricated in a 90-nm CMOS technology and it's area measured to be about 32.4 µm × 32.4 µm only per amplifier.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114490289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An FPGA implementation of the time domain deadbeat algorithm for control applications 用于控制应用的时域无差拍算法的FPGA实现
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397839
B. Alecsa, A. Onea
{"title":"An FPGA implementation of the time domain deadbeat algorithm for control applications","authors":"B. Alecsa, A. Onea","doi":"10.1109/NORCHP.2009.5397839","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397839","url":null,"abstract":"This paper proposes a way of implementing a deadbeat controller in FPGA. The focus is on the FPGA implementation of the digital controller. The emphasis is on the software tools for design and simulation of FPGA based hardware for control applications. The FPGA is interfaced to the controlled process by means of serial analog to digital converter (ADC) and digital to analog converter (DAC). The hardware interface to the ADC and DAC is also described. The experimental results present the method application to a case study: control of a DC motor. The main contribution is the method for design and simulation of control hardware implemented in FPGA.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130545233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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