An FPGA implementation of the time domain deadbeat algorithm for control applications

Abstract

This paper proposes a way of implementing a deadbeat controller in FPGA. The focus is on the FPGA implementation of the digital controller. The emphasis is on the software tools for design and simulation of FPGA based hardware for control applications. The FPGA is interfaced to the controlled process by means of serial analog to digital converter (ADC) and digital to analog converter (DAC). The hardware interface to the ADC and DAC is also described. The experimental results present the method application to a case study: control of a DC motor. The main contribution is the method for design and simulation of control hardware implemented in FPGA.