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A review of dynamic power management methods in NoC under emerging design considerations 基于新兴设计考虑的NoC动态电源管理方法综述
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397823
L. Guang, P. Liljeberg, E. Nigussie, H. Tenhunen
{"title":"A review of dynamic power management methods in NoC under emerging design considerations","authors":"L. Guang, P. Liljeberg, E. Nigussie, H. Tenhunen","doi":"10.1109/NORCHP.2009.5397823","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397823","url":null,"abstract":"A review of dynamic and adaptive techniques for power management of on-chip interconnects, under emerging design considerations, is presented. The progress of IC technology has introduced novel methods, architectures and new challenges for power-aware design exploration. An examination of state-of-the-art power management techniques enables feasible and efficient design of future NoC platforms. This review first analyzes the new challenges, architectures and technologies, including PVT (process, voltage, temperature) variations, rapidly increasing leakage power, multiple on-chip PDN (power delivery network) as well as other architectures, which bring new considerations in low-power design exploration. A wide selection of dynamic power-saving techniques for on-chip interconnects are examined, classified into several categories including run-time datapath configuration, supply configuration and adaptive encoding. The effects and feasibility of these methods, especially their potentials in future technology, are judiciously analyzed. An outlook on generic power management paradigms in next-generation NoCs concludes the review.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114671179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Subthreshold minority-3 gates and inverters used for 32-bit serial and parallel adders implemented in 90 nm CMOS 用于32位串行和并行加法器的亚阈值少数派3门和逆变器在90纳米CMOS中实现
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397845
S. Aunet
{"title":"Subthreshold minority-3 gates and inverters used for 32-bit serial and parallel adders implemented in 90 nm CMOS","authors":"S. Aunet","doi":"10.1109/NORCHP.2009.5397845","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397845","url":null,"abstract":"32-bit serial and parallel adders exploiting minority-3 elements and inverters only, are presented, including chip measurements. The implementation is done in a standard triple-well 90 nm CMOS process. Measurements also demonstrate that the digital abstraction may be maintained for basic building blocks under the presence of stuck-open faults and defect transistors, for a redundancy factor, R, of only 2. R = 2 combined with shorted driven nodes is lower than the traditional R=3 in combination with majority voting.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125156705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High speed data preprocessing for bioimpedance measurements: Architectural exploration 生物阻抗测量的高速数据预处理:建筑学探索
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397838
P. Ellervee, P. Annus, M. Min
{"title":"High speed data preprocessing for bioimpedance measurements: Architectural exploration","authors":"P. Ellervee, P. Annus, M. Min","doi":"10.1109/NORCHP.2009.5397838","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397838","url":null,"abstract":"Measurement of electrical bioimpedance enables to characterize tissues and organs, to get diagnostic images, etc. In this paper, various architectural solutions of digital data preprocessing unit for multichannel bioimpedance analyzer are explored. Extensions for the existing prototype analyzer are discussed keeping in mind performance and cost requirements.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125523887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
MultiCast protocol for SegBus platform SegBus平台的组播协议
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397854
Khalid Latif, H. Tenhunen, T. Seceleanu
{"title":"MultiCast protocol for SegBus platform","authors":"Khalid Latif, H. Tenhunen, T. Seceleanu","doi":"10.1109/NORCHP.2009.5397854","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397854","url":null,"abstract":"The task is to analyze, how different services can be designed for the SegBus multiprocessor platform and observe the improvement in system performance. In this paper, we utilize the concept of broadcasting and multicasting service from standard data bus for multiprocessor systems to enhance the performance of SegBus platform. The running example is represented by the H.264 encoder. The SegBus platform architecture, the communication mechanism, the arbitration scheme, the allocation of processing elements on the platform, and the broadcasting services and their implementation are the main topics analyzed here.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126834114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Implementation aspects of fault-tolerant logic built with single-electron devices 用单电子器件构建的容错逻辑的实现方面
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397816
J. Flak, M. Laiho
{"title":"Implementation aspects of fault-tolerant logic built with single-electron devices","authors":"J. Flak, M. Laiho","doi":"10.1109/NORCHP.2009.5397816","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397816","url":null,"abstract":"This paper presents a single-electron tunneling (SET) device implementation of gates needed to build a nanoscale logic array for fault-tolerant computing. The proposed architecture is based on a regular array of locally interconnected SET gates controlled by CMOS peripheries. Embedded hardware and information redundancies help to surmount the limited reliability of nanodevices. Such a logic system can be versatile due to binary programmable interconnections. Gate structures designed for SET technology are presented and their simulation results are discussed.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128684732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A high-speed and wide detectable frequency range Phase Detector for DLLs 一种用于dll的高速宽检测频率范围鉴相器
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397812
Hadiseh Babazadeh, Arash Esmaili, K. Hadidi
{"title":"A high-speed and wide detectable frequency range Phase Detector for DLLs","authors":"Hadiseh Babazadeh, Arash Esmaili, K. Hadidi","doi":"10.1109/NORCHP.2009.5397812","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397812","url":null,"abstract":"A very simple, low power, wide range and high accuracy Phase Detector (PD) is presented solving many problems of the conventional circuits. SPICE simulation results show that the immune frequency range of operation is 1MHz to 2GHz. The dead zone of the presented open loop PD is zero, makes it the best choice to be used in high speed DLLs. This circuit is tested in 0.35um CMOS technology.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129365968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Thermal analysis of on-chip interconnects in multicore systems 多核系统片上互连的热分析
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397817
Kameswar Rao Vaddina, P. Liljeberg, J. Plosila
{"title":"Thermal analysis of on-chip interconnects in multicore systems","authors":"Kameswar Rao Vaddina, P. Liljeberg, J. Plosila","doi":"10.1109/NORCHP.2009.5397817","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397817","url":null,"abstract":"As the temperature increases, interconnect delay increases due to the linear increase in electrical resistivity. This degrades the performance and shortens the interconnects life time. Package reliability will also be severely affected by the resulting thermal hotspots, thus impacting the overall performance of multicore systems. We approach this challenge by proposing to use thermal management techniques with the help of architectural thermal model of a multicore system running on a network with interconnects spawning across it. In this regard we have analysed the spatial thermal profile of the global Cu nanowire for on-chip interconnects in 65nm CMOS technology from ST microelectronics. The average temperature rise ΔT due to signaling, along the length of the conductor has been found to be around 6.8°C for a global interconnection link. The impact of this temperature rise along the interconnects has been analysed with two different signal transmission systems namely current-mode and voltage-mode signaling.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129580570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Symmetric semi-floating-gate pseudo differential pair for low-voltage analog design 用于低压模拟设计的对称半浮栅伪差分对
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397850
Y. Berg
{"title":"Symmetric semi-floating-gate pseudo differential pair for low-voltage analog design","authors":"Y. Berg","doi":"10.1109/NORCHP.2009.5397850","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397850","url":null,"abstract":"In this paper we present a symmetric ultra low-voltage pseudo differential pair based on a clocked semi floating-gate transistor. The clocked semi floating-gate transistors are exploited to increase the current level for ultra low supply voltages and may be used in ultra low voltage mixed signal design. The pseudo differential pair may operate at supply voltages down to 250mV. Simulated data for 90nm CMOS process is included.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"10 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114339613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
NoC Interface for fault-tolerant Message-Passing communication on Multiprocessor SoC platform 多处理器SoC平台上容错消息传递通信的NoC接口
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397848
H. Kariniemi, J. Nurmi
{"title":"NoC Interface for fault-tolerant Message-Passing communication on Multiprocessor SoC platform","authors":"H. Kariniemi, J. Nurmi","doi":"10.1109/NORCHP.2009.5397848","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397848","url":null,"abstract":"A prevalent design paradigm in electronic systems design is the usage of multiple programmable processors on general purpose Multiprocessor System-on-Chip (MPSoC) platforms where processors and other sub-systems communicate through communication infrastructures called Network-on-Chip (NoC). This paper presents a new approach to a NoC Interface (NI) called Micronswitch Interface (MSI) designed for message-passing communication with a light-weight Micron Message-Passing (MMP) protocol on Micronmesh MPSoC platform. The operation of the MSI Hardware (HW) and Software (SW) are tightly coupled with that of the MMP protocol in order to improve communication performance. The MSI provides mechanisms for efficient buffer management and fault-tolerant communication which will be necessary for reliable and efficient operation of the MPSoCs. Performance analyses show that the MSI is also able to produce a good throughput and latency.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114476041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Device modelling for 60 GHz radio front-ends in 65 nm CMOS 60 GHz射频前端65纳米CMOS器件建模
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397803
S. Tao, S. Rodriguez, A. Rusu, M. Ismail
{"title":"Device modelling for 60 GHz radio front-ends in 65 nm CMOS","authors":"S. Tao, S. Rodriguez, A. Rusu, M. Ismail","doi":"10.1109/NORCHP.2009.5397803","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397803","url":null,"abstract":"This paper presents an electromagnetic simulation-based modelling solution for active and passive devices which targets 60 GHz front-end integrated circuits. An EM model, using existing transistor compact models as core, is developed to account for the parasitic elements due to wiring stacks. A spiral inductor lumped model, based on EM simulation S-parameter data is also derived. The models are process and layout dependent, which have been verified by the design of a low noise amplifier in a 60 GHz radio front-end.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126518049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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