Thermal analysis of on-chip interconnects in multicore systems

Abstract

As the temperature increases, interconnect delay increases due to the linear increase in electrical resistivity. This degrades the performance and shortens the interconnects life time. Package reliability will also be severely affected by the resulting thermal hotspots, thus impacting the overall performance of multicore systems. We approach this challenge by proposing to use thermal management techniques with the help of architectural thermal model of a multicore system running on a network with interconnects spawning across it. In this regard we have analysed the spatial thermal profile of the global Cu nanowire for on-chip interconnects in 65nm CMOS technology from ST microelectronics. The average temperature rise ΔT due to signaling, along the length of the conductor has been found to be around 6.8°C for a global interconnection link. The impact of this temperature rise along the interconnects has been analysed with two different signal transmission systems namely current-mode and voltage-mode signaling.