用于低压模拟设计的对称半浮栅伪差分对

2009 NORCHIP Pub Date : 2009-11-01 DOI:10.1109/NORCHP.2009.5397850

Y. Berg

{"title":"用于低压模拟设计的对称半浮栅伪差分对","authors":"Y. Berg","doi":"10.1109/NORCHP.2009.5397850","DOIUrl":null,"url":null,"abstract":"In this paper we present a symmetric ultra low-voltage pseudo differential pair based on a clocked semi floating-gate transistor. The clocked semi floating-gate transistors are exploited to increase the current level for ultra low supply voltages and may be used in ultra low voltage mixed signal design. The pseudo differential pair may operate at supply voltages down to 250mV. Simulated data for 90nm CMOS process is included.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"10 4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Symmetric semi-floating-gate pseudo differential pair for low-voltage analog design\",\"authors\":\"Y. Berg\",\"doi\":\"10.1109/NORCHP.2009.5397850\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we present a symmetric ultra low-voltage pseudo differential pair based on a clocked semi floating-gate transistor. The clocked semi floating-gate transistors are exploited to increase the current level for ultra low supply voltages and may be used in ultra low voltage mixed signal design. The pseudo differential pair may operate at supply voltages down to 250mV. Simulated data for 90nm CMOS process is included.\",\"PeriodicalId\":308859,\"journal\":{\"name\":\"2009 NORCHIP\",\"volume\":\"10 4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 NORCHIP\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NORCHP.2009.5397850\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 NORCHIP","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORCHP.2009.5397850","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

本文提出了一种基于时钟半浮栅晶体管的对称超低电压伪差分对。利用时钟半浮栅晶体管提高超低电源电压下的电流水平，可用于超低电压混合信号设计。伪差分对可以在低至250mV的电源电压下工作。文中还包括了90nm CMOS工艺的模拟数据。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Symmetric semi-floating-gate pseudo differential pair for low-voltage analog design

In this paper we present a symmetric ultra low-voltage pseudo differential pair based on a clocked semi floating-gate transistor. The clocked semi floating-gate transistors are exploited to increase the current level for ultra low supply voltages and may be used in ultra low voltage mixed signal design. The pseudo differential pair may operate at supply voltages down to 250mV. Simulated data for 90nm CMOS process is included.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2009 NORCHIP

自引率

0.00%

发文量