2009 NORCHIP最新文献

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Simulation-based verification of power aware System-on-Chip designs using UPF IEEE 1801 基于UPF IEEE 1801的功耗感知片上系统设计的仿真验证
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397836
C. Trummer, C. M. Kirchsteiger, C. Steger, R. Weiss, D. Dalton, M. Pistauer
{"title":"Simulation-based verification of power aware System-on-Chip designs using UPF IEEE 1801","authors":"C. Trummer, C. M. Kirchsteiger, C. Steger, R. Weiss, D. Dalton, M. Pistauer","doi":"10.1109/NORCHP.2009.5397836","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397836","url":null,"abstract":"For System-on-Chips (SoCs) the most critical design constraint is power dissipation. Therefore, power aware design should be introduced at early stages of SoC design where it has the highest benefits for power reduction. This also lowers the design complexity and verification effort. Until recently, capabilities to describe and verify the power design early were inadequate which often led to late re-design. Lately, the IEEE 1801 Standard for Design and Verification of Low Power Integrated Circuits, an extension of the Unified Power Format (UPF) was approved. This work uses the new IEEE 1801 standard to describe power aware design. The power design is automatically translated into an executable hierarchy parallel to the system design. Simulation results from system and power design are used to automatically verify the SoC's power aware design against its specifications.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116093829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A 1–5 GHz UWB low noise amplifier in 0.18 µm CMOS 1 - 5ghz超宽带低噪声放大器,0.18µm CMOS
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397799
M. Shen, T. Tong, J. Mikkelsen, O. K. Jensen, T. Larsen
{"title":"A 1–5 GHz UWB low noise amplifier in 0.18 µm CMOS","authors":"M. Shen, T. Tong, J. Mikkelsen, O. K. Jensen, T. Larsen","doi":"10.1109/NORCHP.2009.5397799","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397799","url":null,"abstract":"A 1–5 GHz ultra-wideband CMOS low-noise amplifier (LNA) is presented. A common-gate topology is adopted for the input stage to achieve wideband input matching, while a cascode stage is used as the second stage to provide power gain at high frequencies. By using two inductors in the LNA, a small chip area is obtained. The LNA has been fabricated in a standard 0.18 µm CMOS technology. The measured maximum power gain is 13.7 dB, and the noise figure is 5.0–6.5 dB in the frequency band of 1–5 GHz. The measured third order (two-tone) input intercept point (IIP3) is −9.8 dBm at 4 GHz. The LNA consumes 9 mW with a 1.8 V supply, and occupies an area of 0.78 mm2.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114266147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Efficient network interface architecture for network-on-chips 片上网络的高效网络接口架构
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397837
M. Ebrahimi, M. Daneshtalab, N. P. Sreejesh, P. Liljeberg, H. Tenhunen
{"title":"Efficient network interface architecture for network-on-chips","authors":"M. Ebrahimi, M. Daneshtalab, N. P. Sreejesh, P. Liljeberg, H. Tenhunen","doi":"10.1109/NORCHP.2009.5397837","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397837","url":null,"abstract":"In this paper, we present novel network interface architecture for on-chip networks to increase memory parallelism and to improve the resource utilization. The proposed architecture exploits AXI transaction based protocol to be compatible with existing IP cores. Experimental results with synthetic test case demonstrate that the proposed architecture outperforms the conventional architecture in term of latency.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124851287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Low-power, enhanced-gain adaptive-biasing-based Operational Transconductance Amplifiers 低功耗、增益增强自适应偏置型运算跨导放大器
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397853
T. Cao, D. Wisland, T. Lande, F. Moradi
{"title":"Low-power, enhanced-gain adaptive-biasing-based Operational Transconductance Amplifiers","authors":"T. Cao, D. Wisland, T. Lande, F. Moradi","doi":"10.1109/NORCHP.2009.5397853","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397853","url":null,"abstract":"A symmetrical PMOS OTA (Operational Transconductance Amplifier) is used to build an advanced rail-to-rail amplifier with improved DC-gain and reduced power consumption. By using the adaptive biasing circuit for two differential inputs, a low stand-by current can be achieved, reducing power consumption, while the DC-gain of the proposed OTA is improved by adding a partial feedback loop. Simulation shows that the OTA has a low static power consumption of 57.6 µW and a high FoM of 5.13 [(V/µs.pF)/µW] for a load capacitor of 10pF. The circuit is designed in a STM 90nm CMOS process.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129551089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A simplified router architecture for the modified Fat Tree Network-on-Chip topology 一种简化的路由器架构,用于改进的胖树片上网络拓扑结构
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397806
A. Bouhraoua, O. Diraneyya, M. Elrabaa
{"title":"A simplified router architecture for the modified Fat Tree Network-on-Chip topology","authors":"A. Bouhraoua, O. Diraneyya, M. Elrabaa","doi":"10.1109/NORCHP.2009.5397806","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397806","url":null,"abstract":"The architecture of the class of routers to implement the modified Fat Tree topology is shown. The router architecture is buffer-less with a simplified routing function. The routing function is obtained from a model that describes the Fat Tree topology and from where the equations governing the routing circuitry are derived. A parameterized router model is developed and coded in verilog. A modified Fat Tree network generator that uses the router model is also developed. The generator produces verilog files directly used in functional simulation.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121635236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
CBSC pipelined ADC with comparator preset, and comparator delay compensation 具有比较器预置和比较器延迟补偿的CBSC流水线ADC
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397846
C. Wulff, T. Ytterdal
{"title":"CBSC pipelined ADC with comparator preset, and comparator delay compensation","authors":"C. Wulff, T. Ytterdal","doi":"10.1109/NORCHP.2009.5397846","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397846","url":null,"abstract":"We present a differential comparator-based switched-capacitor (CBSC) pipelined ADC with comparator preset, and comparator delay compensation. Compensating for the comparator delay by digitally adjusting the comparator threshold improves the ADC resolution 23 times. The ADC is manufactured in a 90nm CMOS technology. The ADC core is 0.85mm × 0.35mm, with a 1.2V supply for the core and 1.8V for the input switches. The ADC has an effective number of bits (ENOB) of 7.05-bit, and a power dissipation of 8.5mW at 60MS/s.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121312365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Message routing in 3D networks-on-chip 三维片上网络中的消息路由
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397855
C. Rusu, L. Anghel, D. Avresky
{"title":"Message routing in 3D networks-on-chip","authors":"C. Rusu, L. Anghel, D. Avresky","doi":"10.1109/NORCHP.2009.5397855","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397855","url":null,"abstract":"Nowadays 3D chips are fabricated by stacking 2D layers and manufacturing vertical links between them. In this paper we present a routing scheme suited for 3D networks-on-chip (NoCs). It is based on the reuse of existing routing schemes for 2D NoCs. Our 3D scheme is scalable and can be used with any 2D topology. The effectiveness of the scheme for intra-layer communication is given by the respective 2D routing scheme of each layer, while for the inter-layer communication the scheme can always find a route between any source and destination, if there is one available.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126928368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A current reused oscillator-mixer for DS-UWB 一种用于DS-UWB的电流复用振荡器混频器
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397797
T. Koivisto, E. Tiiliharju
{"title":"A current reused oscillator-mixer for DS-UWB","authors":"T. Koivisto, E. Tiiliharju","doi":"10.1109/NORCHP.2009.5397797","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397797","url":null,"abstract":"In this paper, we propose a quadrature oscillator-mixer combination. This circuit reuses the bleeding current, which relaxes mixer design trade-offs noise, linearity and gain at low supply voltages, by replacing the bleed current source as an oscillator. The linearized merged oscillator-mixer achieves a 8 dB gain, −4 dBV IIP3 and 6.5 dB white noise figure at the 7 GHz frequency. The phase-noise of the quadrature oscillator is −97 dBc/Hz at the 1 MHz offset from the 7Ghz LO frequency. The circuit consumes 10 mA from a 1.2 V supply.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127057090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The rules have changed 规则变了
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397859
K. Martin
{"title":"The rules have changed","authors":"K. Martin","doi":"10.1109/NORCHP.2009.5397859","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397859","url":null,"abstract":"Over the last five years, there have been a number of paradigm changes in sub-micron analog circuit design that have significantly changed the game; for example, most analog IC designs involve using IP blocks; realizing complete chips all in-house is just too large a task for a single company to take on; rather, chip realization is more an operation of consolidation of the designs of others; a difficult and error-prone process. Practically, all sub-micron analog designs have extensive digital circuitry for programmability, calibration, test, start-up, etc.; analog designers must also be digital designers. Current digital synthesis flows are geared towards having a single large sea of gates; this doesn't work well for divide-and-conquer and a number of disparate blocks from different providers, with different flows and methodologies. Simulating mixed-mode designs is often more challenging and time consuming than actually doing the designs. Analog designers must also be programmers. Most IP blocks need to be customized for particular applications. If test is not built in, the chances of having a production worthy chip in less than two iterations is small. With a complete mask set often costing more than $1 million, having a large chip not work because of a small analog IP block from a ‘Mom-and-Pop’ IP producer does not make economic sense; however, large IP providers are too big to customize individual designs. Many chips fail because of poor or incorrect communication of required register values and programming requirements; there is no standardization. The ‘necessary tools’ cost upwards of $1 million initial cost and $500K per year operating costs, for sub-micron designs, yet individual IP blocks may sell for only $75K, can easily take 18 months to develop by a complete group, and have few economies of scale. Most designers spend most of their time supporting legacy designs and porting designs to other technologies (and in meetings at larger companies).","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125307356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
1V transimpedance amplifier in 90nm CMOS for medical ultrasound imaging 用于医学超声成像的90nm CMOS 1V跨阻放大器
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397833
Linga Reddy Cenkeramaddi, T. Ytterdal
{"title":"1V transimpedance amplifier in 90nm CMOS for medical ultrasound imaging","authors":"Linga Reddy Cenkeramaddi, T. Ytterdal","doi":"10.1109/NORCHP.2009.5397833","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397833","url":null,"abstract":"In this paper we present the measurement results of a 1V transimpedance amplifier designed in a 90nm CMOS technology as an analog front-end for Capacitive Micro machined Ultrasound Transducers (CMUTs) for medical ultrasound imaging. The proposed amplifier is designed to amplify the signals from 15MHz to 45MHz with a center frequency of 30MHz. The measurements show that the proposed amplifier achieves a voltage gain of 15.5 dB, an output noise power spectral density of 0.0497 (µV)/SQRT(Hz) at a center-frequency of 30 MHz, and a total harmonic distortion of −28.8 dB, at 400mV p-p output voltage at 30 MHz input signal frequency. It draws only 450 µA current from a 1-V power supply. The proposed transimpedance amplifier was fabricated in a 90-nm CMOS technology as it is intended for intravenous medical ultrasound imaging, which demands smaller area for the front-end amplifiers. Area measured to be about 26 µm × 26 µm only per amplifier.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127560454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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