具有比较器预置和比较器延迟补偿的CBSC流水线ADC

2009 NORCHIP Pub Date : 2009-11-01 DOI:10.1109/NORCHP.2009.5397846

C. Wulff, T. Ytterdal

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引用次数: 10

摘要

我们提出了一种基于差分比较器的开关电容(CBSC)流水线ADC，具有比较器预置和比较器延迟补偿功能。通过数字调节比较器阈值来补偿比较器延迟，可将ADC分辨率提高23倍。该ADC采用90纳米CMOS技术制造。ADC芯为0.85mm × 0.35mm，芯为1.2V电源，输入开关为1.8V电源。该ADC的有效位数(ENOB)为7.05位，60MS/s时的功耗为8.5mW。

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CBSC pipelined ADC with comparator preset, and comparator delay compensation

We present a differential comparator-based switched-capacitor (CBSC) pipelined ADC with comparator preset, and comparator delay compensation. Compensating for the comparator delay by digitally adjusting the comparator threshold improves the ADC resolution 23 times. The ADC is manufactured in a 90nm CMOS technology. The ADC core is 0.85mm × 0.35mm, with a 1.2V supply for the core and 1.8V for the input switches. The ADC has an effective number of bits (ENOB) of 7.05-bit, and a power dissipation of 8.5mW at 60MS/s.

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2009 NORCHIP

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