{"title":"The rules have changed","authors":"K. Martin","doi":"10.1109/NORCHP.2009.5397859","DOIUrl":null,"url":null,"abstract":"Over the last five years, there have been a number of paradigm changes in sub-micron analog circuit design that have significantly changed the game; for example, most analog IC designs involve using IP blocks; realizing complete chips all in-house is just too large a task for a single company to take on; rather, chip realization is more an operation of consolidation of the designs of others; a difficult and error-prone process. Practically, all sub-micron analog designs have extensive digital circuitry for programmability, calibration, test, start-up, etc.; analog designers must also be digital designers. Current digital synthesis flows are geared towards having a single large sea of gates; this doesn't work well for divide-and-conquer and a number of disparate blocks from different providers, with different flows and methodologies. Simulating mixed-mode designs is often more challenging and time consuming than actually doing the designs. Analog designers must also be programmers. Most IP blocks need to be customized for particular applications. If test is not built in, the chances of having a production worthy chip in less than two iterations is small. With a complete mask set often costing more than $1 million, having a large chip not work because of a small analog IP block from a ‘Mom-and-Pop’ IP producer does not make economic sense; however, large IP providers are too big to customize individual designs. Many chips fail because of poor or incorrect communication of required register values and programming requirements; there is no standardization. The ‘necessary tools’ cost upwards of $1 million initial cost and $500K per year operating costs, for sub-micron designs, yet individual IP blocks may sell for only $75K, can easily take 18 months to develop by a complete group, and have few economies of scale. Most designers spend most of their time supporting legacy designs and porting designs to other technologies (and in meetings at larger companies).","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 NORCHIP","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORCHP.2009.5397859","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Over the last five years, there have been a number of paradigm changes in sub-micron analog circuit design that have significantly changed the game; for example, most analog IC designs involve using IP blocks; realizing complete chips all in-house is just too large a task for a single company to take on; rather, chip realization is more an operation of consolidation of the designs of others; a difficult and error-prone process. Practically, all sub-micron analog designs have extensive digital circuitry for programmability, calibration, test, start-up, etc.; analog designers must also be digital designers. Current digital synthesis flows are geared towards having a single large sea of gates; this doesn't work well for divide-and-conquer and a number of disparate blocks from different providers, with different flows and methodologies. Simulating mixed-mode designs is often more challenging and time consuming than actually doing the designs. Analog designers must also be programmers. Most IP blocks need to be customized for particular applications. If test is not built in, the chances of having a production worthy chip in less than two iterations is small. With a complete mask set often costing more than $1 million, having a large chip not work because of a small analog IP block from a ‘Mom-and-Pop’ IP producer does not make economic sense; however, large IP providers are too big to customize individual designs. Many chips fail because of poor or incorrect communication of required register values and programming requirements; there is no standardization. The ‘necessary tools’ cost upwards of $1 million initial cost and $500K per year operating costs, for sub-micron designs, yet individual IP blocks may sell for only $75K, can easily take 18 months to develop by a complete group, and have few economies of scale. Most designers spend most of their time supporting legacy designs and porting designs to other technologies (and in meetings at larger companies).