The rules have changed

K. Martin
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引用次数: 4

Abstract

Over the last five years, there have been a number of paradigm changes in sub-micron analog circuit design that have significantly changed the game; for example, most analog IC designs involve using IP blocks; realizing complete chips all in-house is just too large a task for a single company to take on; rather, chip realization is more an operation of consolidation of the designs of others; a difficult and error-prone process. Practically, all sub-micron analog designs have extensive digital circuitry for programmability, calibration, test, start-up, etc.; analog designers must also be digital designers. Current digital synthesis flows are geared towards having a single large sea of gates; this doesn't work well for divide-and-conquer and a number of disparate blocks from different providers, with different flows and methodologies. Simulating mixed-mode designs is often more challenging and time consuming than actually doing the designs. Analog designers must also be programmers. Most IP blocks need to be customized for particular applications. If test is not built in, the chances of having a production worthy chip in less than two iterations is small. With a complete mask set often costing more than $1 million, having a large chip not work because of a small analog IP block from a ‘Mom-and-Pop’ IP producer does not make economic sense; however, large IP providers are too big to customize individual designs. Many chips fail because of poor or incorrect communication of required register values and programming requirements; there is no standardization. The ‘necessary tools’ cost upwards of $1 million initial cost and $500K per year operating costs, for sub-micron designs, yet individual IP blocks may sell for only $75K, can easily take 18 months to develop by a complete group, and have few economies of scale. Most designers spend most of their time supporting legacy designs and porting designs to other technologies (and in meetings at larger companies).
规则变了
在过去的五年中,亚微米模拟电路设计发生了许多范式变化,这些变化极大地改变了游戏规则;例如,大多数模拟IC设计涉及使用IP块;对于一家公司来说,在内部实现完整的芯片是一项艰巨的任务;更确切地说,芯片实现更多的是一种整合他人设计的操作;这是一个困难且容易出错的过程。实际上,所有亚微米模拟设计都具有广泛的数字电路,用于可编程,校准,测试,启动等;模拟设计师也必须是数字设计师。目前的数字合成流程是为了拥有一个单一的大门海洋;这对于分而治之和来自不同提供者、具有不同流和方法的大量不同块并不适用。模拟混合模式设计通常比实际设计更具挑战性和耗时。模拟设计师也必须是程序员。大多数IP块需要为特定的应用程序定制。如果没有内置测试,那么在不到两次迭代中获得具有生产价值的芯片的机会很小。一个完整的掩模套件通常要花费100多万美元,让一个大芯片因为一个小的模拟IP块而无法工作,这在经济上是不合理的;然而,大型IP提供商规模太大,无法定制个性化设计。许多芯片失败是因为所需的寄存器值和编程要求的通信不佳或不正确;没有标准化。对于亚微米设计,“必要工具”的初始成本高达100万美元,每年的运营成本高达50万美元,而单个IP块的售价可能仅为7.5万美元,一个完整的团队可能需要18个月的时间才能开发完成,而且规模经济效益很低。大多数设计师将大部分时间花在支持遗留设计和将设计移植到其他技术上(以及在大公司的会议上)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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