M. Shen, T. Tong, J. Mikkelsen, O. K. Jensen, T. Larsen
{"title":"1 - 5ghz超宽带低噪声放大器，0.18µm CMOS","authors":"M. Shen, T. Tong, J. Mikkelsen, O. K. Jensen, T. Larsen","doi":"10.1109/NORCHP.2009.5397799","DOIUrl":null,"url":null,"abstract":"A 1–5 GHz ultra-wideband CMOS low-noise amplifier (LNA) is presented. A common-gate topology is adopted for the input stage to achieve wideband input matching, while a cascode stage is used as the second stage to provide power gain at high frequencies. By using two inductors in the LNA, a small chip area is obtained. The LNA has been fabricated in a standard 0.18 µm CMOS technology. The measured maximum power gain is 13.7 dB, and the noise figure is 5.0–6.5 dB in the frequency band of 1–5 GHz. The measured third order (two-tone) input intercept point (IIP3) is −9.8 dBm at 4 GHz. The LNA consumes 9 mW with a 1.8 V supply, and occupies an area of 0.78 mm2.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 1–5 GHz UWB low noise amplifier in 0.18 µm CMOS\",\"authors\":\"M. Shen, T. Tong, J. Mikkelsen, O. K. Jensen, T. Larsen\",\"doi\":\"10.1109/NORCHP.2009.5397799\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1–5 GHz ultra-wideband CMOS low-noise amplifier (LNA) is presented. A common-gate topology is adopted for the input stage to achieve wideband input matching, while a cascode stage is used as the second stage to provide power gain at high frequencies. By using two inductors in the LNA, a small chip area is obtained. The LNA has been fabricated in a standard 0.18 µm CMOS technology. The measured maximum power gain is 13.7 dB, and the noise figure is 5.0–6.5 dB in the frequency band of 1–5 GHz. The measured third order (two-tone) input intercept point (IIP3) is −9.8 dBm at 4 GHz. The LNA consumes 9 mW with a 1.8 V supply, and occupies an area of 0.78 mm2.\",\"PeriodicalId\":308859,\"journal\":{\"name\":\"2009 NORCHIP\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 NORCHIP\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NORCHP.2009.5397799\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 NORCHIP","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORCHP.2009.5397799","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1–5 GHz ultra-wideband CMOS low-noise amplifier (LNA) is presented. A common-gate topology is adopted for the input stage to achieve wideband input matching, while a cascode stage is used as the second stage to provide power gain at high frequencies. By using two inductors in the LNA, a small chip area is obtained. The LNA has been fabricated in a standard 0.18 µm CMOS technology. The measured maximum power gain is 13.7 dB, and the noise figure is 5.0–6.5 dB in the frequency band of 1–5 GHz. The measured third order (two-tone) input intercept point (IIP3) is −9.8 dBm at 4 GHz. The LNA consumes 9 mW with a 1.8 V supply, and occupies an area of 0.78 mm2.
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