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A multirate Sigma Delta modulator for GSM standard in CMOS technology CMOS技术中GSM标准的多速率Sigma Delta调制器
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397820
M. Laguna, R. Viladoms, F. Colodro, A. Torralba
{"title":"A multirate Sigma Delta modulator for GSM standard in CMOS technology","authors":"M. Laguna, R. Viladoms, F. Colodro, A. Torralba","doi":"10.1109/NORCHP.2009.5397820","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397820","url":null,"abstract":"A multirate 3rd order modulator targeting GSM standard is presented in this paper. Dynamic Element Matching technique to improve the linearity for the 4-bit DAC in the external feedback path is described. High-level simulations give a maximum SNDR of 79.98 dB while simulation results for a prototype made in a standard 0.6 µm CMOS technology show that the SNDR at the transistor level achieves 78.47 dB including 1% of mismatch, proving a good response of the 4-bit DAC with Dynamic Element Matching technique included.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116204628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Benefits of decomposing wide CMOS transistors into minimum-size gates 将宽CMOS晶体管分解成最小尺寸栅极的好处
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397795
Hans Kristian Otnes Berge, S. Aunet
{"title":"Benefits of decomposing wide CMOS transistors into minimum-size gates","authors":"Hans Kristian Otnes Berge, S. Aunet","doi":"10.1109/NORCHP.2009.5397795","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397795","url":null,"abstract":"In this paper we show how decomposition of a wide CMOS transistor into a multi-finger FET with gates of minimum size can be beneficial for the reduction of delay and power-delay products in logic gates. This design possibility, which we call a minimum-split transistor (MST), seems to be largely overlooked in the literature. In a 90 nm CMOS process we compare the design to wide transistors. By exploiting the narrow-width effect, reduced parasitic capacitances from a shorter active channel and increased gate-drain spacing, we achieve up to 75–85% higher operation speed at a similar or reduced power consumption. The worst-case timing delay is reduced by 35–40% along with the nominal values. The design technique is considered valuable, in particular for critical time paths. The paper takes the perspective of subthreshold logic design at 200 mV, but the technique is also useful above threshold. A statistical experiment also investigates how Vth variation in MSTs changes with the number of parallell gates.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116008620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Analytical derivation of traffic patterns in shared memory architectures from Task Graphs 从任务图中分析导出共享内存架构中的流量模式
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397825
M.B. Stuart, J. Sparsø
{"title":"Analytical derivation of traffic patterns in shared memory architectures from Task Graphs","authors":"M.B. Stuart, J. Sparsø","doi":"10.1109/NORCHP.2009.5397825","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397825","url":null,"abstract":"Task Graphs is a commonly used application model in research in computer-aided design tools for design space exploration of embedded systems, including system synthesis, scheduling and application mapping. These design tools need an estimate of the actual communication in the target system caused by the application modelled by the task graph. In this paper, we present a method for analytically deriving the worst-case traffic pattern when a task graph is mapped to a multiprocessor system-on-chip with a shared memory architecture. We describe the additionally needed information besides the dependencies in the task graph in order to derive the traffic pattern. Finally, we construct a simulator that we use to find the actual traffic pattern in a system and compare this to the derived pattern. Results show that our worst-case derivation overestimates the bandwidth by 9% for systems with small caches and between 32% and 52% for systems with large caches.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131945310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Electromagnetic impulse radio camera 电磁脉冲无线电照相机
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397835
M. Z. Dooghabadi, Tuan-Anh Vu, S. Sudalaiyandi, H. A. Hjortland, T. Lande, O. Naess, S. Hamran
{"title":"Electromagnetic impulse radio camera","authors":"M. Z. Dooghabadi, Tuan-Anh Vu, S. Sudalaiyandi, H. A. Hjortland, T. Lande, O. Naess, S. Hamran","doi":"10.1109/NORCHP.2009.5397835","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397835","url":null,"abstract":"An UWB impulse radio programmable transmitter array is presented, usable for electromagnetic beamforming. The linear antenna array may be programmed for focal beamforming using seven impulse radio transmitters. Two different spatial configurations are evaluated for use as beam scanning electronics of an electromagnetic camera. A novel high-precision, programmable delay element is explored for accurate beam control. Measured results shows that the scan line of the beamformer can be steered with sufficient resolution facilitating an electromagnetic CMOS camera.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132588330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hardware implementation of an SVD based MIMO OFDM channel estimator 基于SVD的MIMO OFDM信道估计器的硬件实现
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397840
J. Lofgren, Shahid Mehmood, Nadir Khan, Babar Masood, M. Irfan Z. Awan, Imran Khan, N. A. Chisty, Peter Nilsson
{"title":"Hardware implementation of an SVD based MIMO OFDM channel estimator","authors":"J. Lofgren, Shahid Mehmood, Nadir Khan, Babar Masood, M. Irfan Z. Awan, Imran Khan, N. A. Chisty, Peter Nilsson","doi":"10.1109/NORCHP.2009.5397840","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397840","url":null,"abstract":"This paper presents a hardware design of an SVD based channel estimator. The details of the design are explained and some key aspects are discussed. The design has been implemented and tested on an FPGA and synthesized for an ASIC in 130 nm technology. It is shown that it is possible to get a clock frequency of 179 MHz for a 1.38 mm2 design. This corresponds to ~30 M estimates per second, which is more than needed in current wireless systems. Further, simulations show that this design would consume an average power of around 8.5 mW with a peak power at 14.2 mW. The presented data shows that it is possible to use these kind of advanced channel estimation strategies in wireless receivers, even though there has been no prior reports of these being implemented.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129818062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Prospects for building cortex-scale CMOL/CMOS circuits: A design space exploration 构建皮质尺度CMOL/CMOS电路的前景:设计空间探索
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397858
D. Hammerstrom, M. Zaveri
{"title":"Prospects for building cortex-scale CMOL/CMOS circuits: A design space exploration","authors":"D. Hammerstrom, M. Zaveri","doi":"10.1109/NORCHP.2009.5397858","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397858","url":null,"abstract":"In this paper, we briefly present a hardware design space exploration methodology to investigate various architectures/designs, and their relative performance/price trade-offs. Using this methodology, we investigate CMOS and hybrid nano-scale (CMOL) based digital and mixed-signal circuits that implement Bayesian Memory (a simplified computational model based on George and Hawkins' model of the visual cortex, and Pearl's belief propagation), and for a cortex-scale spiking neural model. We then present the results of the hardware design space exploration, for implementing large-scale neuro/cortex inspired systems, and provide ballpark performance/price and scaling estimates for the same. These results provide some insight into the prospects for building large-scale Bayesian Inference engines, and neuromorphic networks using emerging nanoelectronics and/or nanogrid circuit structures. In general, the study of such hypothetical architectures will help guide research trends in intelligent computing (including neuro/cognitive systems), and the use of radical new device and circuit technology in these systems.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"2009 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127334966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques 基于集合导向数值技术的CMOS逻辑标准单元晶体管尺寸多目标优化
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397800
Matthias W. Blesken, Ulrich Rückert, Dominik Steenken, K. Witting, M. Dellnitz
{"title":"Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques","authors":"Matthias W. Blesken, Ulrich Rückert, Dominik Steenken, K. Witting, M. Dellnitz","doi":"10.1109/NORCHP.2009.5397800","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397800","url":null,"abstract":"The design of resource efficient integrated circuits (IC) requires solving a minimization problem of more than one objective given as measures of available resources. This multiobjective optimization problem (MOP) can be solved on the smallest unit, the standard cells, to improve the performance of the entire IC. The traditional way of sizing the transistors of a standard logic cell does not focus on the resources directly. In this work transistor sizing is approached via an MOP and solved by set-oriented numerical techniques. A comparison of the Pareto optimal designs to elements of a commercial standard cell library indicates that for some gates the performance can even be significantly improved.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129415377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
FPGA implementation of autocorrelation-based feature detector for cognitive radio 基于自相关的认知无线电特征检测器的FPGA实现
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397849
K. Kokkinen, V. Turunen, M. Kosunen, S. Chaudhari, V. Koivunen, J. Ryynanen
{"title":"FPGA implementation of autocorrelation-based feature detector for cognitive radio","authors":"K. Kokkinen, V. Turunen, M. Kosunen, S. Chaudhari, V. Koivunen, J. Ryynanen","doi":"10.1109/NORCHP.2009.5397849","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397849","url":null,"abstract":"Cognitive radio is an emerging technology in communication systems. Cognitive radios aim to relief the shortage of spectral resources by identifying and exploiting underutilized radio spectrum. A key task of the cognitive radio is spectrum sensing in order to find free spectrum and detect licensed spectrum user transmissions. In this paper, an FPGA implementation of a feature detector for OFDM-based primary user signals is presented. The detection algorithm, that was originally presented in , is modified in order to achieve power and area efficient hardware realization. The algorithm is implemented in an FPGA evaluation environment, and the performance is verified in simulation.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115235311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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