K. Kokkinen, V. Turunen, M. Kosunen, S. Chaudhari, V. Koivunen, J. Ryynanen
{"title":"FPGA implementation of autocorrelation-based feature detector for cognitive radio","authors":"K. Kokkinen, V. Turunen, M. Kosunen, S. Chaudhari, V. Koivunen, J. Ryynanen","doi":"10.1109/NORCHP.2009.5397849","DOIUrl":null,"url":null,"abstract":"Cognitive radio is an emerging technology in communication systems. Cognitive radios aim to relief the shortage of spectral resources by identifying and exploiting underutilized radio spectrum. A key task of the cognitive radio is spectrum sensing in order to find free spectrum and detect licensed spectrum user transmissions. In this paper, an FPGA implementation of a feature detector for OFDM-based primary user signals is presented. The detection algorithm, that was originally presented in , is modified in order to achieve power and area efficient hardware realization. The algorithm is implemented in an FPGA evaluation environment, and the performance is verified in simulation.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"193 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 NORCHIP","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORCHP.2009.5397849","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Cognitive radio is an emerging technology in communication systems. Cognitive radios aim to relief the shortage of spectral resources by identifying and exploiting underutilized radio spectrum. A key task of the cognitive radio is spectrum sensing in order to find free spectrum and detect licensed spectrum user transmissions. In this paper, an FPGA implementation of a feature detector for OFDM-based primary user signals is presented. The detection algorithm, that was originally presented in , is modified in order to achieve power and area efficient hardware realization. The algorithm is implemented in an FPGA evaluation environment, and the performance is verified in simulation.