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Power efficient cross-correlation using bitstreams 使用比特流的高效交叉相关
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397844
O.E. Liseth, D. Mo, H. A. Hjortland, T. Lande, D. Wisland
{"title":"Power efficient cross-correlation using bitstreams","authors":"O.E. Liseth, D. Mo, H. A. Hjortland, T. Lande, D. Wisland","doi":"10.1109/NORCHP.2009.5397844","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397844","url":null,"abstract":"The fundamental operation of cross-correlating signals is viable in a number of signal processing applications. In typical pattern-matching applications, cross-correlation is desirable. In this paper we present a power efficient implementation of a time-domain cross-correlator suitable for integration in CMOS. Bitstream coding of both data and template simplify multiplication operations. Measured performance of a CMOS implementation in 90 nm technology is reported.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122606412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Event control and programming for microprocessor peripheral systems 微处理器外围系统的事件控制和编程
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397807
Rune André Bjørnerud, Morten W. Lund, K. Svarstad
{"title":"Event control and programming for microprocessor peripheral systems","authors":"Rune André Bjørnerud, Morten W. Lund, K. Svarstad","doi":"10.1109/NORCHP.2009.5397807","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397807","url":null,"abstract":"Standard microcontrollers waste a significant amount of CPU cycles in order to handle I/O and peripheral resources. To handle communication between on-chip peripherals without interference from CPU, DMA or interrupt resources, the Atmel® AVR® XMEGA¿ 1 microcontroller introduces a peripheral resource known as the Event System. The Event System currently implemented on the AVR XMEGA offers limited resources for logical event computation, and can be used as a basic routing facility for I/O and peripipheral signals. The present work proposes a novel extension to the Event System. In order to enhance routing flexibility a programmable asynchronous interconnect topology with pipelined switches has been designed, leading to increased computational power through the use of asynchronous LUTs to handle logical event computations.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125425862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On-chip offset generator for A/D converter INL testing without an accurate test stimulus 片上偏置发生器用于A/D转换器INL测试，无需精确的测试刺激
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397847
Esa Korhonen, J. Kostamovaara
{"title":"On-chip offset generator for A/D converter INL testing without an accurate test stimulus","authors":"Esa Korhonen, J. Kostamovaara","doi":"10.1109/NORCHP.2009.5397847","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397847","url":null,"abstract":"Means of testing the integral nonlinearity (INL) of A/D converters (ADCs) without an accurate test stimulus have recently been proposed. These methods are based on a constant DC offset between two low-quality test signals. We describe here an on-chip offset generator and analyse its limitations. Experimental tests show that it can be used to test the INL of 12-b ADCs.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"157 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120969150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On the impact of buffer size on packet loss in adaptable network-on-chips for runtime reconfigurable system-on-chips 面向运行时可重构片上系统的自适应片上网络中缓冲区大小对丢包的影响
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397798
C. Albrecht, R. Koch, Thilo Pionteck
{"title":"On the impact of buffer size on packet loss in adaptable network-on-chips for runtime reconfigurable system-on-chips","authors":"C. Albrecht, R. Koch, Thilo Pionteck","doi":"10.1109/NORCHP.2009.5397798","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397798","url":null,"abstract":"This paper explores the interdependencies between buffer size, throughput, latency and packet loss in runtime adaptable network-on-chips. Based on the SystemC simulation model of a runtime reconfigurable system-on-chip, buffer sizes of switches and of network interfaces were adjusted to find the optimal relation between throughput, latency and packet loss. A synthetic traffic generator parameterised according to characteristics of traffic patterns in networking applications provides the stimulus for the simulation. Simulation results show that buffers for only a few packets are required within the system while most buffer memory should be provided at the system gateway.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117257736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 65-nm CMOS ultra-low-power LC quadrature VCO 65纳米CMOS超低功耗LC正交压控振荡器
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397805
K. Lee, C. Bryant, M. Tormanen, H. Sjöland
{"title":"A 65-nm CMOS ultra-low-power LC quadrature VCO","authors":"K. Lee, C. Bryant, M. Tormanen, H. Sjöland","doi":"10.1109/NORCHP.2009.5397805","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397805","url":null,"abstract":"An ultra-low-power LC quadrature VCO (QVCO) is presented. It is designed in a single-poly seven-metal 65 nm CMOS process. To minimize power dissipation an inductor with a high LQ product of 188 nH at 2.4 GHz, and a self-resonant frequency (fo) of 3.8 GHz, was designed. According to SpectreRF simulations the power dissipation is below 250 ¿W at a 0.6V supply. At this supply the simulated tuning range and phase noise at 1 MHz offset are 10.4% (2.34-2.59 GHz) and -113.4 dBc/Hz respectively. The phase noise figure of merit (FoM) is better than 187 dB at all supply voltages of interest, which is competitive to other state-of-the-art QVCOs.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129043464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Design considerations of 8 mm3 reconfigurable computing platform 8 mm3可重构计算平台的设计考虑
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397834
Karri Nikunen, H. Heusala, J. Komulainen
{"title":"Design considerations of 8 mm3 reconfigurable computing platform","authors":"Karri Nikunen, H. Heusala, J. Komulainen","doi":"10.1109/NORCHP.2009.5397834","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397834","url":null,"abstract":"this paper presents a new ideology, and preliminary design calculations of a generic object of modern, digital system component. In this design scenario, system consists of multiple objects. All the objects are small-scaled, using low power which enables self-production of the used energy. All the objects have multi-channel radio, and a FPGA, functioning as a core of the reconfigurable object. In the beginning, every object is a generic, containing basic configuration stored into them. When needed, objects can be specialized to function in a specific behaviour. Swarm of these objects can be adapted to work in various forms. When needed, part, or the whole architecture can be changed. This paper describes construction of first generation energy independent generic smart object.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124084465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-power subthreshold to above threshold level shifter in 90 nm process 90nm工艺低功耗亚阈值到高于阈值的电平移位器
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397793
Amir Hasanbegovic, S. Aunet
{"title":"Low-power subthreshold to above threshold level shifter in 90 nm process","authors":"Amir Hasanbegovic, S. Aunet","doi":"10.1109/NORCHP.2009.5397793","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397793","url":null,"abstract":"The use of multiple voltage domains in an integrated circuit has been widely utilized with the aim of finding a tradeoff between power saving and performance. Level shifters allow for effective interfacing between voltage domains supplied by different voltage levels. In this paper we present a low power level shifters in the 90nm technology node capable of converting subthreshold voltage signals to above threshold voltage signals. The level shifter makes use of MTCMOS design technique which gives more design flexibility, especially in low power systems. Post layout simulations indicate low power consumption and low energy consumption across process-, mismatch- and temperature variations. Minimum input voltage attainable while maintaining robust operation is found to be around 180mV, at maximum frequency of 1MHz. The level shifter employs an enable/disable feature, allowing for power saving when the level shifter is not in use.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129901183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
A dual feedback loop low-noise amplifier 双反馈回路低噪声放大器
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397852
E. Tiiliharju, T. Koivisto
{"title":"A dual feedback loop low-noise amplifier","authors":"E. Tiiliharju, T. Koivisto","doi":"10.1109/NORCHP.2009.5397852","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397852","url":null,"abstract":"This paper studies application of a semi-active dual loop feedback network in an ultrawideband low-noise amplifier which has been realized in a 130-nm bulk digital CMOS process. The proposed simple feedback connection is shown to improve amplifier stability and to increase isolation, with no discernible extra cost. Measurement results support the stated benefits with stable amplifier operation in all measurement points.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130974484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Ultra low power application specific instruction-set processor design for a cardiac beat detector algorithm 一种用于心跳检测算法的超低功耗专用指令集处理器设计
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397828
Y. H. Yassin, P. G. Kjeldsberg, J. Hulzink, I. Romero, J. Huisken
{"title":"Ultra low power application specific instruction-set processor design for a cardiac beat detector algorithm","authors":"Y. H. Yassin, P. G. Kjeldsberg, J. Hulzink, I. Romero, J. Huisken","doi":"10.1109/NORCHP.2009.5397828","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397828","url":null,"abstract":"High efficiency and low power consumption are among the main topics in embedded systems today. For complex applications, off-the-shelf processor cores might not provide the desired goals in terms of power consumption. By optimizing the processor for the application, one can improve the computing power by introducing special purpose hardware units. In this paper, we present a case study with a possible design methodology for an ultra low power application specific instruction-set processor. A cardiac beat detector algorithm based on the Continuous Wavelet Transform is implemented in the C language. This application is further optimized using several software power optimization techniques. The resulting application is mapped on a basic processor architecture provided by Target Compiler Technologies, and the processor is further optimized for ultra low power consumption by applying application specific hardware, and by using several hardware optimization techniques. The optimized processor is compared with the unoptimized version, resulting in a 55% reduction in power consumption. The reduction in the total execution cycle count is 81%. Power gating, and dynamic voltage and frequency scaling, are investigated for further power optimization. For a given case, the reduction in the already optimized power consumption is estimated to be 62% and 35%, respectively.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131074105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Static ultra low voltage CMOS logic 静态超低电压CMOS逻辑
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397792
Y. Berg
{"title":"Static ultra low voltage CMOS logic","authors":"Y. Berg","doi":"10.1109/NORCHP.2009.5397792","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397792","url":null,"abstract":"In this paper we examine a quasi static and a static ultra low-voltage precharge CMOS logic. The static ultra low-voltage logic can be used to design high speed and energy efficient CMOS circuits. Using the proposed circuit technique the static current consumption can controlled and the logic style is suitable for large logic depth, i.e. serial adders. The delay of a static ultra low-voltage gate can be reduced to less than 10% compared to a static complementary gate.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115454587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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