Static ultra low voltage CMOS logic

Abstract

In this paper we examine a quasi static and a static ultra low-voltage precharge CMOS logic. The static ultra low-voltage logic can be used to design high speed and energy efficient CMOS circuits. Using the proposed circuit technique the static current consumption can controlled and the logic style is suitable for large logic depth, i.e. serial adders. The delay of a static ultra low-voltage gate can be reduced to less than 10% compared to a static complementary gate.